AD9915 AD [Analog Devices], AD9915 Datasheet - Page 35

• Manufacturer Part Number: AD9915
• Description: 2.5 GSPS Direct Digital Synthesizer with 12-Bit DAC
• Manufacturer: AD [Analog Devices]

Data Sheet
The synchronization mechanism begins with the clock
distribution and delay equalization block, which is used to
ensure that all devices receive an edge-aligned REF_CLK signal.
However, even though the REF_CLK signal is edge aligned
among all devices, this alone does not guarantee that the clock
state of each internal clock generator is coordinated with the
others. This is the role of the synchronization redistribution
circuit, which accepts the SYNC_OUT signal generated by the
master device and redistributes it to the SYNC_IN input of the
slave units (as well as feeding it back to the master). The goal of
the redistributed SYNC_OUT signal from the master device is
to deliver an edge-aligned SYNC_IN signal to all of the sync
receivers. Assuming that all devices share the same REF_CLK
edge (due to the clock distribution and delay equalization
block) and all devices share the same SYNC_IN edge (due to
the synchronization distribution and delay equalization block),
all devices should generate an internal sync pulse in unison and
the synchronized sync pulses cause all of the devices to assume
the same predefined clock state simultaneously; that is, the
internal clocks of all devices become fully synchronized. The
synchronization mechanism depends on the reliable generation
of a sync pulse by the edge detection block in the sync receiver.
Generation of a valid sync pulse, however, requires proper
sampling of the rising edge of the SYNC_IN signal with the
rising edge of the local SYSCLK. If the edge timing of these
signals fails to meet the setup or hold time requirements of the
internal latches in the edge detection circuitry, the proper
generation of the sync pulse is in jeopardy.
Ambient operating temperature and self-heating of the
must also be considered when attempting to synchronize
AT REF_CLK
ALIGNED
INPUTS
EDGE
Figure 49. Configuration of Multiple Devices to Be Synchronized
FPGA
FPGA
FPGA
DELAY EQUALIZATION
CLOCK DISTRIBUTION
(FOR EXAMPLE AD951x)
AND
AD9915
DATA
DATA
DATA
Rev. A | Page 35 of 48
SYNC
SYNC
SYNC
NUMBER 1
NUMBER 2
NUMBER 3
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IN
IN
IN
REF_CLK
REF_CLK
REF_CLK
SOURCE
CLOCK
SYNC
SYNC
SYNC
OUT
OUT
OUT
multiple devices. In general, the propagation delay from the
SYNC_IN pin to the internal clock generators is fixed for a
given operating temperature. However, large temperature
differences between devices or rapid increases in device
temperature at power-up increase the complexity of
synchronization.
Table 14 and Table 15 display the delay time increment for both
SYNC_IN and SYNC_OUT vs. their corresponding register
values, from 0 to 7.
Table 14. SYNC_IN Delay (Total Delay = 1.2 ns)
Delay Step
0 to 1
1 to 2
2 to 3
3 to 4
4 to 5
5 to 6
6 to 7
Table 15. SYNC_OUT Delay (Total Delay = 1.97 ns)
Delay Step
0 to 1
1 to 2
2 to 3
3 to 4
4 to 5
5 to 6
6 to 7
MASTER DEVICE
AT SYNC_IN
ALIGNED
INPUTS
EDGE
DELAY EQUALIZATION
(FOR EXAMPLE AD951x)
SYNCHRONIZATION
DISTRIBUTION AND
Increment, Typ (ns)
0.26
0.15
0.15
0.15
0.15
0.17
0.17
Increment, Typ (ns)
0.17
0.3
0.3
0.3
0.3
0.3
0.3
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