AD9915 AD [Analog Devices], AD9915 Datasheet - Page 36

• Manufacturer Part Number: AD9915
• Description: 2.5 GSPS Direct Digital Synthesizer with 12-Bit DAC
• Manufacturer: AD [Analog Devices]

REGISTER MAP AND BIT DESCRIPTIONS
Table 16. Register Map
Register
Name (Serial
Address)
CFR1—
CFR2—
CFR3—
CFR4—
Digital Ramp
AD9915
Control
Function
Register 1
(0x00)
Control
Function
Register 2
(0x01)
Control
Function
Register 3
(0x02)
Control
Function
Register 4
(0x03)
Lower Limit
Register
(0x04)
Bit Range
(Parallel
Address)
[7:0]
(0x00)
[15:8]
(0x01)
[23:16]
(0x02)
[31:24]
(0x03)
[7:0]
(0x04)
[15:8]
(0x05)
[23:16]
(0x06)
[31:24]
(0x07)
[7:0]
(0x08)
[15:8]
(0x09)
[23:16]
(0x0A)
[31:24]
(0x0B)
[7:0]
(0x0C)
[15:8]
(0x0D)
[23:16]
(0x0E)
[31:24]
(0x0F)
[7:0]
(0x10)
[15:8]
(0x11)
[23:16]
(0x12)
[31:24]
(0x13)
Bit 7
(MSB)
Digital
power-
down
Load LRR
at I/O
update
Matched
latency
enable
Profile
mode
enable
Open
Open
Bit 6
DAC
power-
down
Autoclear
digital
ramp
accumu-
lator
Frequency
jump
enable
Parallel
data port
enable
Manual I
selection
Input
divider
reset
CP
Bit 5
REF CLK
input
power-
down
Autoclear
phase
accumu-
lator
DRG over
output
enable
Digital ramp destination
Input divider[1:0]
Open
Requires register default value settings (0x20)
Requires register default value settings (0x31)
Requires register default value settings (0x05)
Rev. A | Page 36 of 48
Open
Bit 4
Open
Clear digital
ramp
accumulator
Open
Digital ramp lower limit[23:16]
Digital ramp lower limit[31:24]
Digital ramp lower limit[15:8]
Digital ramp lower limit[7:0]
I
Feedback Divider N[7:0]
CP
Open
[2:0]
Open
Open
Open
Bit 3
External
power-down
control
Clear phase
accumulator
SYNC_CLK
enable
Digital ramp
enable
Doubler
enable
Bit 2
Open
Open
SYNC_CLK
invert
Digital
ramp no-
dwell high
Lock
detect
enable
PLL enable
Auxiliary
divider
power-
down
Bit 1
SDIO input
only
External
OSK enable
Parallel port
streaming
enable
SYNC_OUT
enable
Digital
ramp no-
dwell low
PLL ref
disable
DAC CAL
clock
power-
down
Minimum LDW[1:0]
SYNC out/
in mux
enable
Program
modulus
enable
Doubler
clock edge
DAC CAL
enable
Bit 0
(LSB)
LSB first
mode
OSK
enable
Enable
sine
output
VCO cal
enable
Data Sheet
2
Default
Value
(Hex)
0x08
0x00
0x01
0x00
0x00
0x09
0x00
0x00
0x1C
0x19
0x00
0x00
0x20
0x31
0x05
0x00
0x00
0x00
0x00
0x00
1