AD9915 AD [Analog Devices], AD9915 Datasheet - Page 42

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AD9915

Manufacturer Part Number
AD9915
Description
2.5 GSPS Direct Digital Synthesizer with 12-Bit DAC
Manufacturer
AD [Analog Devices]
Datasheet

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Bits
9
8
7
6
5
4
3
2
1
0
Control Function Register 2 (CFR2)—Address 0x01
Table 18. Bit Descriptions for CFR2
Bit(s)
[31:24]
23
22
[21:20]
19
18
17
16
15
14
13
AD9915
Mnemonic
External OSK enable
OSK enable
Digital power-down
DAC power-down
REFCLK input power-down
Open
External power-down control
Open
SDIO input only
LSB first mode
Mnemonic
Open
Profile mode enable
Parallel data port enable
Digital ramp destination
Digital ramp enable
Digital ramp no-dwell high
Digital ramp no-dwell low
Programmable modulus
enable
Matched latency enable
Frequency jump enable
DRG over output enable
Description
0 = manual OSK enabled (default).
1 = automatic OSK enabled.
Ineffective unless CFR1[8] = 1.
0 = OSK disabled (default).
1 = OSK enabled. To engage any digital amplitude adjust using DRG, profile, or direct mode via
the 32-bit parallel port, or OSK pin, this bit must be set.
This bit is effective without the need for an I/O update.
0 = clock signals to the digital core are active (default).
1 = clock signals to the digital core are disabled.
0 = DAC clock signals and bias circuits are active (default).
1 = DAC clock signals and bias circuits are disabled.
This bit is effective without the need for an I/O update.
0 = REFCLK input circuits and PLL are active (default).
1 = REFCLK input circuits and PLL are disabled.
Open.
0 = assertion of the EXT_PWR_DWN pin affects power-down (default).
1 = assertion of the EXT_PWR_DWN pin affects fast recovery power-down.
Open.
0 = configures the SDIO pin for bidirectional operation; 2-wire serial programming
mode (default).
1 = configures the serial data I/O pin (SDIO) as an input only pin; 3-wire serial
programming mode.
0 = configures the serial I/O port for MSB-first format (default).
1 = configures the serial I/O port for LSB-first format.
Description
Open
0 = disables profile mode functionality (default).
1 = enables profile mode functionality. Profile pins are used to select the desired profile.
See the Parallel Data Port Modulation Mode section for more details.
0 = disables parallel data port modulation functionality (default).
1 = enables parallel data port modulation functionality.
See Table 9 for details. Default is 00. See the Digital Ramp Generator (DRG) section for more
details.
0 = disables digital ramp generator functionality (default).
1 = enables digital ramp generator functionality.
See the Digital Ramp Generator (DRG) section for details.
0 = disables no-dwell high functionality (default).
1 = enables no-dwell high functionality.
See the Digital Ramp Generator (DRG) section for details.
0 = disables no-dwell low functionality (default).
1 = enables no-dwell low functionality.
0 = disables programmable modulus.
1 = enables programmable modulus.
0 = simultaneous application of amplitude, phase, and frequency changes to the DDS arrive at
the output in the order listed in Table 2 under data latency (pipe line delay)(default).
1 = simultaneous application of amplitude, phase, and frequency changes to the DDS arrive at
the output simultaneously.
0 = disables frequency jump.
1 = enables frequency jump mode. Must have the digital generator DRG enabled for this
feature.
0 = disables the DROVER output.
1 = enables the DROVER output.
Rev. A | Page 42 of 48
Data Sheet

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