AD9915 AD [Analog Devices], AD9915 Datasheet - Page 46

• Manufacturer Part Number: AD9915
• Description: 2.5 GSPS Direct Digital Synthesizer with 12-Bit DAC
• Manufacturer: AD [Analog Devices]

Profile Registers
There are 16 serial I/O addresses (Address 0x0B to Address
0x01A) dedicated to device profiles. Eight of the 16profiles
house up to eight single tone frequencies. The remaining eight
profiles contain the corresponding phase offset and amplitude
Profile 0 to Profile 7, Single Tone Registers—0x0B, 0x0D, 0x0F, 0x11, 0x13, 0x15, 0x17, 0x19
Four bytes are assigned to each register.
Table 28. Bit Descriptions for Profile 0 to Profile 7 Single Tone Registers
Bit(s)
[31:0]
Profile 0 to Profile 7, Phase Offset and Amplitude Registers—0x0C, 0x0E, 0x10, 0x12, 0x14, 0x16, 0x18, 0x1A
Four bytes are assigned to each register.
Table 29. Bit Descriptions for Profile 0 to Profile 7 Phase Offset and Amplitude Registers
Bit(s)
[31:28]
[27:16]
[15:0]
USR0 Register—Address 0x1B
Table 30. Bit Descriptions for USR0 Register
Bit(s)
[31:25]
24
[23:8]
7
6
[5:3]
[2:0]
AD9915
Mnemonic
Frequency tuning word
Mnemonic
Open
Amplitude scale factor
Phase offset word
Mnemonic
Open
PLL lock
(See description)
Reserved
CAL with SYNC
SYNC_OUT delay ADJ
SYNC_IN delay ADJ
Description
This 32-bit number controls the DDS frequency.
Description
Open.
This 12-bit word controls the DDS frequency. Note that the OSK enable bit (0x00[8]) must
be set to logic high to make amplitude adjustments.
This 16-bit word controls the DDS frequency.
Description
This is a readback bit only. If Logic 1 is read back, the PLL is locked. Logic 0 represents a
nonlocked state.
These bits must always be programmed with the default values listed in the default column
in Table 16.
Must be kept at Logic 0 (default).
0 = a SYNC_IN signal is not required to calibrate the DAC clock.
1 = a SYNC_IN signal is required to calibrate the DAC clock.
Provides the ability to delay the SYNC_OUT signal for multichip synchronization purposes.
Provides the ability to delay the internal SYNC_IN signal for multichip synchronization
purposes.
Rev. A | Page 46 of 48
parameters relative to the profile pin setting. To enable profile
mode, set the profile mode enable bit in CFR2 (0x01[23]) = 1.
The active profile register is selected using the external PS[2:0]
pins.
Data Sheet