ADF4108BRUZ AD [Analog Devices], ADF4108BRUZ Datasheet

ADF4108BRUZ

Manufacturer Part Number

ADF4108BRUZ

Description

PLL Frequency Synthesizer

Manufacturer

AD [Analog Devices]

Datasheet

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FEATURES

8.0 GHz bandwidth

3.2 V to 3.6 V power supply

Separate charge pump supply (V

Programmable, dual modulus prescaler 8/9, 16/17, 32/33, or

Programmable charge pump currents

Programmable antibacklash pulse width

3-wire serial interface

Analog and digital lock detect

Hardware and software power-down mode

Loop filter design possible with ADIsimPLL

APPLICATIONS

Broadband wireless access

Satellite systems

Instrumentation

Wireless LANs

Base stations for wireless radio

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registered trademarks are the property of their respective owners.

voltage in 3.3 V systems

64/65

REF

DATA

CLK

24-BIT INPUT

OUT

PRESCALER

FUNCTION

LATCH

P/P + 1

FROM

N = BP + A

AGND DGND

) allows extended tuning

A, B COUNTER

R COUNTER

FUNCTION

LATCH

14-BIT

LOAD

B COUNTER

A COUNTER

FUNCTIONAL BLOCK DIAGRAM

13-BIT

6-BIT

Figure 1.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

Fax: 781.461.3113

GENERAL DESCRIPTION

The ADF4108 frequency synthesizer can be used to implement

local oscillators in the up-conversion and down-conversion

sections of wireless receivers and transmitters. It consists of a

low noise digital PFD (phase frequency detector), a precision

charge pump, a programmable reference divider, programmable

A and B counters, and a dual-modulus prescaler (P/P + 1). The

A (6-bit) and B (13-bit) counters, in conjunction with the dual-

modulus prescaler (P/P + 1), implement an N divider (N =

BP + A). In addition, the 14-bit reference counter (R counter),

allows selectable REFIN frequencies at the PFD input. A

complete phase-locked loop (PLL) can be implemented if the

synthesizer is used with an external loop filter and voltage

controlled oscillator (VCO). Its very high bandwidth means

that frequency doublers can be eliminated in many high

frequency systems, simplifying system architecture and

reducing cost.

FREQUENCY

DETECTOR

DETECT

PLL Frequency Synthesizer

CPGND

PHASE

LOCK

OUT

CPI3 CPI2 CPI1

SETTING 1

CURRENT

M3 M2 M1

MUX

REFERENCE

CHARGE

PUMP

ADF4108

CPI6 CPI5 CPI4

HIGH Z

SETTING 2

CURRENT

SET

ADF4108

MUXOUT

www.analog.com

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