AD9915 AD [Analog Devices], AD9915 Datasheet
AD9915
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AD9915 Summary of contents
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... LINEAR SWEEP 2.5GSPS DDS CORE BLOCK REF CLK TIMING AND CONTROL SERIAL OR PARALLEL DATA PORT Figure 1. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 Fax: 781.461.3113 with 12-Bit DAC AD9915 12-BIT DAC www.analog.com ©2012 Analog Devices, Inc. All rights reserved. ...
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... AD9915 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 General Description ......................................................................... 3 Specifications ..................................................................................... 4 DC Specifications ......................................................................... 4 AC Specifications .......................................................................... 5 Absolute Maximum Ratings ............................................................ 8 Thermal Performance .................................................................. 8 ESD Caution .................................................................................. 8 Pin Configuration and Function Descriptions ............................. 9 Typical Performance Characteristics ........................................... 12 Equivalent Circuits ......................................................................... 16 Theory of Operation ...................................................................... 17 Single Tone Mode ....................................................................... 17 Profile Modulation Mode .......................................................... 17 Digital Ramp Modulation Mode ...
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... AD9915 amplitude tuning words. The AD9915 temperature range (see the Absolute Maximum Ratings section). AD9915 also AD9915 DDS AMPLITUDE (A) Acos (ωt + θ) A PHASE (θ) θ ...
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... AD9915 SPECIFICATIONS DC SPECIFICATIONS AVDD (1.8V) and DVDD (1.8V) = 1.8 V ± 5%, AVDD (3.3V) and DVDD_I/O (3.3V) = 3.3 V ± 5 mA, external reference clock frequency = 2.5 GHz with reference clock (REF CLK) multiplier bypassed, unless otherwise noted. OUT Table 1. Parameter Min SUPPLY VOLTAGE DVDD_I/O 3.135 DVDD 1.71 AVDD (3.3V) 3.135 AVDD (1.8V) 1.71 SUPPLY CURRENT ...
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... SYSCLK cycles 152 µ SYNC_CLK period Rev Page AD9915 = 25° 3.3 kΩ SET OUT Test Conditions/Comments Input frequency range Maximum f is 0.4 × f OUT SYSCLK Equivalent to 316 mV swing on each leg 10 pF load CFR2 register, Bit ...
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... AD9915 Parameter PARALLEL PORT TIMING Write Timing WR Address Setup Time to Active Address Hold Time to WR Inactive Data Setup Time to WR Inactive Data Hold Time to WR Inactive WR Minimum Low Time WR Minimum High Time Minimum WR Time Read Timing Address to Data Valid RD Address Hold to ...
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... Sweep Mode Frequency Phase Amplitude Min Typ Max Unit 320 SYSCLK cycles 296 SYSCLK cycles 104 SYSCLK cycles 296 SYSCLK cycles 272 SYSCLK cycles 80 SYSCLK cycles 392 SYSCLK cycles 368 SYSCLK cycles 176 SYSCLK cycles Rev Page AD9915 Test Conditions/Comments ...
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... AD9915 ABSOLUTE MAXIMUM RATINGS Table 3. Parameter AVDD (1.8V), DVDD (1.8V) Supplies AVDD (3.3V), DVDD_I/O (3.3V) Supplies Digital Input Voltage Digital Output Current Storage Temperature Range Operating Temperature Range Maximum Junction Temperature Lead Temperature (10 sec Soldering) Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only ...
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... Parallel Port Pin/Address Line. Multipurpose pin depending on the state of the function pins (F0 to F3). The state of the function pins determines if this pin acts as a line for direct FSK, PSK, or ASK data address line for programming the internal registers. Rev Page AD9915 66 OSK 65 DROVER 64 DRHOLD ...
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... AD9915 Pin No. Mnemonic I/O 12 D8/A0 I/O 18 D4/SYNCIO I 19 D3/SDO I/O 20 D2/SDIO/WR I/O 21 D1/SCLK/ D0/CS/PWD I 6, 23, 73 DVDD (1.8V 17, 24, 74, 84 DGND I 16, 83 DVDD_I/O (3.3V) I 32, 56, 57 AVDD (1.8V) I 33, 35, 37, 38, AGND I 44, 46, 49, 51 34, 36, 39, 40, AVDD (3.3V) I 43, 47, 50, 52, 53, 60 25, 26, 27 PS0 to PS2 I 28, 29, 30 ...
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... Master Reset. Digital input (active high). Clears all memory elements and sets registers to default values. Input/Output Update. Digital input (active high). A high on this pin transfers the contents of the I/O buffers to the corresponding internal registers. Exposed Pad. The EPAD must be soldered to ground. Rev Page AD9915 ...
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... AD9915 TYPICAL PERFORMANCE CHARACTERISTICS Nominal supply voltage; DAC R = 3.3 kΩ, T SET 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 START 0Hz 125MHz/DIV Figure 4. Wideband SFDR at 122.5 MHz SYSCLK = 2.5 GHz (SYSCLK PLL Bypassed) 0 –10 –20 –30 –40 –50 –60 –70 – ...
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... Rev Page CENTER 978.214MHz 50kHz/DIV SPAN 500kHz Figure 13. Narrow-Band SFDR at 978.2 MHz, SYSCLK = 2.5 GHz (SYSCLK PLL Bypassed) SMA AND ADCLK925 SMA 100 1k 10k 100k 1M FREQUENCY OFFSET (Hz) ADCLK925 978MHz 497MHz 305MHz 123MHz 100 1k 10k 100k 1M FREQUENCY OFFSET (Hz) AD9915 10M 100M AD9915 10M 100M ...
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... AD9915 –70 –80 –90 –100 –110 978MHz –120 –130 –140 NORMALIZED –150 REF CLK SOURCE –160 –170 10 100 1k 10k 100k FREQUENCY OFFSET (Hz) Figure 16. Absolute Phase Noise Curves of Normalized REF CLK Source to DDS Output at 978.5 MHz (SYSCLK = 2.5 GHz) –60 –70 –80 –90 – ...
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... Rev Page 930 920 910 900 890 880 870 –6 –4 – TIME (ms) Figure 24. Measured Rising Linear Frequency Sweep 930 920 910 900 890 880 870 –6 –4 – TIME (ms) Figure 25. Measured Falling Linear Frequency Sweep AD9915 ...
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... AD9915 EQUIVALENT CIRCUITS AGND I FS CURRENT SWITCH SWITCH CONTROL ARRAY CODE CODE AOUT 42 INTERNAL INTERNAL 50Ω 50Ω AVDD (3.3V) Figure 26. DAC Output AVDD (3.3V) REF_CLK REF_CLK Figure 27. REF CLK input CURRENT SWITCH ARRAY I /2 – CODE AOUT 41 Rev Page Data Sheet DVDD (3 ...
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... DDS is restricted to powers denominator because the phase accumulator is a set of bits as wide as the frequency tuning word (FTW). When in programmable modulus mode, however, the frequency equation is )(FTW + A/B)/ where f /f < ½, 0 ≤ FTW < Rev Page AD9915 ≤ B ≤ 2 – 1, and A < B. ...
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... DDS output, the profile modulation mode has priority over the parallel data port modulation mode. DDS Signal Control Parameters Rev Page ratio of integers )/10, which is 1,288,490,188 (0x4CCCCCCC in 32-bit AD9915 with these values of FTW, A, and B AD9915 has a built-in Data Sheet 32 )/ )/10 ...
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... ASF Amplitude Scale ASF 20 log 12 2 AD9915 is programmed to modulate any of the DDS . This means that the modulation signal exhibits SYSCLK . The impact of these images SYSCLK 12 ANGLE-TO- AMPLITUDE 12 12 (SINE OR COSINE) TO DAC AD9915 (3) ...
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... AD9915 12-BIT DAC OUTPUT The AD9915 incorporates an integrated 12-bit, current output DAC. The output current is delivered as a balanced signal using two outputs. The use of balanced outputs reduces the potential amount of common-mode noise present at the DAC output, offering the advantage of an increased signal-to-noise ratio. An ...
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... VCO cal enable bit in the CFR1 register, 0x00[24], must be asserted. Subsequent VCO calibrations require that the VCO calibration bit be cleared prior to initiating another VCO calibration. VCO calibration must occur before DAC calibration to ensure optimal performance and functionality. Rev Page AD9915 0.1µF REF_CLK 55 PECL, LVPECL, ...
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... AD9915 PLL Charge Pump The charge pump current (I ) value is automatically chosen via CP the VCO calibration process and feedback divider ( 255) value stored in Feedback Divider N[7:0] in the CFR3 register (0x02[15:8]). To manually override the charge pump current value, the manual I selection bit in CFR3 (0x02[6]) CP must be set to Logic 1 ...
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... DIGITAL RAMP GENERATOR (DRG) DRG Overview To sweep phase, frequency, or amplitude from a defined start point to a defined endpoint, a completely digital ramp generator is included in the AD9915. The DRG makes use of eight control register bits, three external pins, and five 32-bit registers (see Figure 36). DIGITAL RAMP ENABLE ...
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... AD9915 DRG Slope Control The core of the DRG is a 32-bit accumulator clocked by a programmable timer. The time base for the timer is the DDS clock, which operates at 1/ The timer establishes the SYSCLK interval between successive updates of the accumulator. The positive (+Δt) and negative (−Δt) slope step intervals are ...
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... Event 12—The autoclear digital ramp accumulator bit is set, which has no effect on the DRG output because the bit is not effective until an I/O update is issued. Rev Page DDS CLOCK CYCLE UPPER LIMIT AD9915 ...
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... AD9915 Event 13—An I/O update registers that the autoclear digital ramp accumulator bit is set, resetting the ramp accumulator. However, with an automatic clear, the ramp accumulator is held in reset for only a single DDS clock cycle. This forces the DRG output to the lower limit, but the ramp accumulator is immedi- ately made available for normal operation. In this example, the DRCTL pin remains Logic 1 ...
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... DAC bias circuitry and the PLL, VCO, and input clock circuitry. Although the fast recovery power-down does not conserve as much power as the full power-down, it allows the device to awaken very quickly from the power-down state. Rev Page AD9915 ...
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... AD9915 PROGRAMMING AND FUNCTION PINS The AD9915 is equipped with a 32-bit parallel port. The 32-bit port is for programming the internal registers of the device in either serial mode or parallel mode as well as allowing for direct modulation control of frequency (FTW), phase (POW), and amplitude (AMP).The state of the external function pins (F0 to Table 10 ...
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... DDS. Note, however, that although AMP[15:0] indicate 16-bit resolution, the actual amplitude resolution is 12 bits. Therefore, only AMP[11:0] provide amplitude control (that is, AMP[15:12] are not used). Rev Page AD9915 DDS 32 FTW FREQUENCY 16 ...
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... FTW, POW, and AMP registers, the IO_UPDATE pin (see Figure 41) adds another layer of flexibility. To accommodate this functionality, the AD9915 provides a register control bit, parallel port streaming enable (0x00[17]). When this bit is set to Logic 1, the parallel port operates without the need for an I/O update ...
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... There are two phases to a serial communications cycle. The first is the instruction phase to write the instruction byte into the AD9915. The instruction byte contains the address of the register to be accessed and defines whether the upcoming data transfer is a write or read operation. ...
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... Figure 42 to Figure 45 is not required. MSB/LSB TRANSFERS The AD9915 (MSB) first or least significant bit (LSB) first data formats. This functionality is controlled by Bit 0 in CFR1 (0x00). The default format is MSB first. If LSB first is active, all data, including the instruction byte, must follow LSB-first convention ...
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... Data Sheet PARALLEL PROGRAMMING (8-/16-BIT) The state of the external function pins (F0 to F3) determine the type of interface used by the AD9915. Pin 28 to Pin 31 are dedicated function pins. To enable the parallel mode interface set Pin 28 to Pin 31 to logic low. Parallel programming consists of eight address lines and either eight or16 bidirectional data lines for read/write operations ...
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... AD9915 all the devices. This concept is shown in Figure 49, in which three AD9915 operating as a master timing unit and the others as slave units. The master device must have its SYNC_IN pin included as part of the synchronization distribution and delay equalization mechanism in order for synchronized with the slave units ...
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... FPGA NUMBER 2 SYNC SYNC IN OUT REF_CLK DATA AD9915 FPGA NUMBER 3 SYNC SYNC IN OUT Figure 49. Configuration of Multiple Devices to Be Synchronized Rev Page Increment, Typ (ns) 0.26 0.15 0.15 0.15 0.15 0.17 0.17 Increment, Typ (ns) 0.17 0.3 0.3 0.3 0.3 0.3 0.3 MASTER DEVICE EDGE ALIGNED AT SYNC_IN INPUTS SYNCHRONIZATION DISTRIBUTION AND DELAY EQUALIZATION (FOR EXAMPLE AD951x) AD9915 ...
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... AD9915 REGISTER MAP AND BIT DESCRIPTIONS Table 16. Register Map Register Bit Range Name (Serial (Parallel Bit 7 Address) Address) (MSB) Bit 6 CFR1— [7:0] Digital DAC Control (0x00) power- power- Function down down Register 1 (0x00) [15:8] Load LRR Autoclear (0x01) at I/O digital update ramp accumu- ...
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... Upper frequency jump point[7:0] Upper frequency jump point[15:8] Upper frequency jump point[23:16] Upper frequency jump point[31:24] Frequency Tuning Word 0[7:0] Frequency Tuning Word 0[15:8] Frequency Tuning Word 0[23:16] Frequency Tuning Word 0[31:24] Rev Page AD9915 Default Value Bit 0 Bit 2 Bit 1 (LSB) (Hex) 0x00 0x00 ...
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... AD9915 Register Bit Range Name (Serial (Parallel Bit 7 Address) Address) (MSB) Bit 6 Profile 0 (P0) [7:0] Phase/ (0x30) Amplitude [15:8] Register (0x31) (0x0C) [23:16] (0x32) [31:24] (0x33) Profile 1 (P1) [7:0] Frequency (0x34) Tuning [15:8] Word 1 (0x35) Register [23:16] (0x0D) (0x36) [31:24] (0x37) Profile 1 (P1) [7:0] Phase/ (0x38) Amplitude [15:8] Register (0x39) (0x0E) ...
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... Phase Offset Word 6[7:0] Phase Offset Word 6[15:8] Amplitude Scale Factor 6[7:0] Open Frequency Tuning Word 7[7:0] Frequency Tuning Word 7[15:8] Frequency Tuning Word 7[23:16] Frequency Tuning Word 7[31:24] Rev Page AD9915 Bit 0 Bit 2 Bit 1 (LSB) Amplitude Scale Factor 4[11:8] Amplitude Scale Factor 5[11:8] Amplitude Scale Factor 6[11:8] Default Value ...
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... AD9915 Register Bit Range Name (Serial (Parallel Bit 7 Address) Address) (MSB) Bit 6 Profile 7 (P7) [7:0] Phase/ (0x68) Amplitude [15:8] Register (0x69) (0x1A) [23:16] (0x6A) [31:24] (0x6B) USR0 (0x1B) [7:0] Reserved CAL with (0x6C) SYNC [15:8] (0x6D) [23:16] (0x6E) [31:24] (0x6F master reset is required after power up. The master reset returns the internal registers to their default values. ...
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... SYNC_CLK normal operation of the DDS phase accumulator (default asynchronous, static reset of the DDS phase accumulator as long as this bit is set. This bit is synchronized with either an I/O update or a PS[2:0] change and the next rising edge of SYNC_CLK. Open. Rev Page AD9915 ...
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... AD9915 Bits Mnemonic 9 External OSK enable 8 OSK enable 7 Digital power-down 6 DAC power-down 5 REFCLK input power-down 4 Open 3 External power-down control 2 Open 1 SDIO input only 0 LSB first mode Control Function Register 2 (CFR2)—Address 0x01 Table 18. Bit Descriptions for CFR2 Bit(s) Mnemonic [31:24] Open 23 Profile mode enable ...
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... Selects the number of REF CLK cycles that the phase error (at the PFD inputs) must remain within before a PLL lock condition can be read back via Bit 24 in Register 0x00 128 REF CLK cycles 01 = 256 REF CLK cycles 10 = 512 REF CLK cycles 11 = 1024 REF CLK cycles Rev Page AD9915 ...
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... AD9915 Control Function Register 4 (CFR4)—Address 0x03 Table 20. Bit Descriptions for DAC Bit(s) Mnemonic [31:27] Open 26 Auxiliary divider power- down 25 DAC CAL clock power-own 24 DAC CAL enable [23:0] (See description) Digital Ramp Lower Limit Register—Address 0x04 This register is effective only if the digital ramp enable bit in the CFR2 register (0x01[19 See the Digital Ramp Generator (DRG) section for details ...
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... Description 32-bit digital upper frequency jump value. Any time the upper frequency jump value is reached during a frequency sweep, the output frequency jumps to the lower frequency value instantaneously and continues frequency sweeping in a phase-continuous manner. Rev Page AD9915 ...
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... AD9915 Profile Registers There are 16 serial I/O addresses (Address 0x0B to Address 0x01A) dedicated to device profiles. Eight of the 16profiles house up to eight single tone frequencies. The remaining eight profiles contain the corresponding phase offset and amplitude Profile 0 to Profile 7, Single Tone Registers—0x0B, 0x0D, 0x0F, 0x11, 0x13, 0x15, 0x17, 0x19 Four bytes are assigned to each register ...
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... Lead Frame Chip Scale Package [LFCSP_VQ] Evaluation Board Rev Page 0.60 MAX PIN INDICATOR 66 1 EXPOSED PAD 6.70 REF BOTTOM VIEW 10.50 REF FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. AD9915 Package Option CP-88-5 CP-88-5 ...
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... AD9915 NOTES ©2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D10837-0-8/12(A) Rev Page Data Sheet ...