AD9915 AD [Analog Devices], AD9915 Datasheet - Page 19

• Manufacturer Part Number: AD9915
• Description: 2.5 GSPS Direct Digital Synthesizer with 12-Bit DAC
• Manufacturer: AD [Analog Devices]

Data Sheet
FUNCTIONAL BLOCK DETAIL
DDS CORE
The direct digital synthesizer (DDS) block generates a reference
signal (sine or cosine based on 0x00[16], the enable sine output
bit). The parameters of the reference signal (frequency, phase,
and amplitude) are applied to the DDS at its frequency, phase
offset, and amplitude control inputs, as shown in Figure 30.
The output frequency (f
frequency tuning word (FTW) at the frequency control input to
the DDS. The relationship among f
where FTW is a 32-bit integer ranging in value from 0 to
2,147,483,647 (2
full 32-bit range. This range constitutes frequencies from dc to
Nyquist (that is, ½ f
The FTW required to generate a desired value of f
by solving Equation 1 for FTW, as given in Equation 2.
where the round(x) function rounds the argument (the value of
x) to the nearest integer. This is required because the FTW is
constrained to be an integer value. For example, for f
41 MHz and f
(0x556AAAAB).
Programming an FTW greater than 2
image that appears at a frequency given by
The relative phase of the DDS signal can be digitally controlled
by means of a 16-bit phase offset word (POW). The phase offset
is applied prior to the angle-to-amplitude conversion block
internal to the DDS core. The relative phase offset (Δθ) is given by
FTW
f
f
OUT
OUT
=
=
=



 −


round
1
SYSCLK
FTW
2
32
31
FTW
2
− 1), which represents the lower half of the
= 122.88 MHz, FTW = 1,433,053,867
32




SYSCLK



2
f
SYSCLK
32



OUT




f
).
SYSCLK
f
SYSCLK
) of the
f
OUT
OUT








AD9915
, FTW, and f
FREQUENCY
AMPLITUDE
31
CONTROL
CONTROL
CONTROL
produces an aliased
OFFSET
DDS SIGNAL CONTROL PARAMETERS
PHASE
is controlled by the
32
SYSCLK
12
16
(for FTW ≥ 2
OUT
DDS_CLK
ACCUMULATOR
OUT
is given by
is found
32
32
=
32-BIT
Figure 30. DDS Block Diagram
D Q
MSB ALIGNED
Rev. A | Page 19 of 48
R
ACCUMULATOR
RESET
(1)
(2)
31
)
32
17
(MSBs)
14
where the upper quantity is for the phase offset expressed as
radian units and the lower quantity as degrees.
To find the POW value necessary to develop an arbitrary Δθ,
solve the preceding equation for POW and round the result (in
a manner similar to that described previously for finding an
arbitrary FTW).
The relative amplitude of the DDS signal can be digitally scaled
(relative to full scale) by means of a 12-bit amplitude scale
factor (ASF). The amplitude scale value is applied at the output
of the angle-to-amplitude conversion block internal to the DDS
core. The amplitude scale is given by
where the upper quantity is amplitude expressed as a fraction of
full scale and the lower quantity is expressed in decibels relative
to full scale.
To find the ASF value necessary for a particular scale factor, solve
Equation 3 for ASF and round the result (in a manner similar
to that described previously for finding an arbitrary FTW).
When the
signal control parameters, the maximum modulation sample
rate is ¼ f
images at multiples of ¼ f
must be considered when using the device as a modulator.
17
CONVERSION
∆
Amplitude
AMPLITUDE
ANGLE-TO-
(SINE OR
COSINE)
θ
=
SYSCLK
AD9915
360
2
π



. This means that the modulation signal exhibits



POW
12
POW
Scale
12
2
2
14
TO DAC
14
is programmed to modulate any of the DDS
12



=



20
ASF
SYSCLK
2
12
log
. The impact of these images



ASF
2
12



AD9915
(3)