AD9915 AD [Analog Devices], AD9915 Datasheet - Page 29

• Manufacturer Part Number: AD9915
• Description: 2.5 GSPS Direct Digital Synthesizer with 12-Bit DAC
• Manufacturer: AD [Analog Devices]

Data Sheet
FUNCTION
The 32-pin parallel port of the
with an independent set of four function pins that control the
functionality of the parallel port. The 32 pins of the parallel port
constitute a 32-bit word designated by Bits[31:0] (31 indicating
the most significant bit (MSB) and 0 indicating the least
significant bit (LSB)), with the four function pins designated as
F[3:0]. The relationship between the function pins, the 32-pin
parallel port, the internal programming registers, and the DDS
control parameters (frequency, phase, and amplitude) is
illustrated in Figure 41. Note that the parallel port operates in
three different modes as defined by the function pins.
The parallel mode is in effect when the logic levels applied to
the function pins are F[3:0] = 0000. This allows the parallel port
to function as a parallel interface providing access to all of the
device programming registers. In parallel mode, the 32-pin port
(Bits[31:0]) is subdivided into three groups with Bits[31:16]
constituting 16 data bits, Bits[15:8] constituting eight address
bits, and Bits[2:0] constituting three control bits. The address
bits target a specific device register, whereas the data bits
constitute the register content. The control bits establish read or
write functionality as well as set the width of the data bus. That
is, the user can select whether the data bus spans 16 bits
(Bits[31:16]) or eight bits (Bits[23:16]). The parallel mode
NOTES
1. AMP[11:0] CONTROLS AMPLITUDE. AMP[15:12] UNUSED.
PARALLEL
PORT PINS
F[3:0] BITS[31:24] BITS[23:16] BITS[15:8]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
PINS
FTW[31:24]
FTW[31:24]
FTW[31:24]
FTW[31:24]
FTW[31:24]
FTW[23:16]
FTW[23:16]
FTW[23:16]
FTW[23:16]
POW[15:8]
FTW[15:8]
AMP[11:8]
FUNCTION PINS AND DIRECT MODE
BITS[31:0] VS. FTW, POW, AMP
32
4
FTW[23:16]
FTW[23:16]
FTW[23:16]
FTW[23:16]
FTW[23:16]
FTW[15:8]
FTW[15:8]
FTW[15:8]
FTW[15:8]
POW[7:0]
FTW[7:0]
AMP[7:0]
PARALLEL MODE
SERIAL MODE
DIRECT MODE
BITS[31:0]
FTW[31:24]
POW[15:8]
FTW[15:8]
AMP[11:8]
FTW[15:8]
FTW[15:8]
FTW[15:8]
FTW[15:8]
F[3:0]
FTW[7:0]
FTW[7:0]
FTW[7:0]
FTW[7:0]
AD9915
FTW[23:16]
POW[15:8]
POW[15:8]
AMP[15:8]
AMP[15:8]
BITS[7:0]
POW[7:0]
POW[7:0]
POW[7:0]
FTW[7:0]
AMP[7:0]
AMP[7:0]
AMP[7:0]
works in conjunction
32
DECODE
SERIAL MODE
PARALLEL MODE
Figure 41. Parallel Port Block Diagram
27
5
SYNC_CLK
DIRECT MODES
8
8
8
32
Rev. A | Page 29 of 48
BITS[31:24]
BITS[23:16]
BITS[15:8]
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
BIT 2
BIT 1
BIT 0
D Q
CK
32
D[15:8]
D[7:0]
16 BITS/8 BITS
A[7:0]
WR
RD
SYNCIO
SDO
SDIO
SCLK
CS
allows the user to write to the device registers at rates of up to
200 MBps using 16-bit data (or 100 MBps using 8-bit data).
The serial mode is in effect when the logic levels applied to the
function pins are F[3:0] = 0001. This allows the parallel port to
function as a serial interface providing access to all of the device
programming registers. In this mode, only five pins of the 32-
pin parallel port are functional (Bits[4:0]). These pins provide
chip select ( CS ), serial clock (SCLK), and I/O synchronization
(SYNCIO) functionality for the serial interface, as well as two
serial data lines (SDO and SDIO). The serial mode supports
data rates of up to 80 Mbps.
When the logic levels applied to the function pins are F[3:0] =
0010 to 1101 (note that 1110 and 1111 are unused), the parallel
port functions as a high speed interface with direct access to the
32-bit frequency, 16-bit phase, and 12-bit amplitude parameters
of the DDS core. The table in Figure 41 shows the segmentation
of the 32-pin parallel port by identifying Bits[31:0] with the
frequency (FTW[31:0]), phase (POW[15:0]), and amplitude
(AMP[15:0]) parameters of the DDS. Note, however, that
although AMP[15:0] indicate 16-bit resolution, the actual
amplitude resolution is 12 bits. Therefore, only AMP[11:0]
provide amplitude control (that is, AMP[15:12] are not used).
PARALLEL
CONTROL
CONTROL
SERIAL
ROUTING
LOGIC
32
16
12
PROGRAMMING
IO_UPDATE
REGISTERS
OSK ENABLE
POW
FTW
AMP
FREQUENCY
PHASE
AMPLITUDE
SYSTEM
CLOCK
DDS
AD9915