AD9915 AD [Analog Devices], AD9915 Datasheet - Page 24

• Manufacturer Part Number: AD9915
• Description: 2.5 GSPS Direct Digital Synthesizer with 12-Bit DAC
• Manufacturer: AD [Analog Devices]

DRG Slope Control
The core of the DRG is a 32-bit accumulator clocked by a
programmable timer. The time base for the timer is the DDS
clock, which operates at 1/24 f
interval between successive updates of the accumulator. The
positive (+Δt) and negative (−Δt) slope step intervals are
independently programmable as given by
where P and N are the two 16-bit values stored in the 32-bit digital
ramp rate register and control the step interval. N defines the step
interval of the negative slope portion of the ramp. P defines the step
interval of the positive slope portion of the ramp.
The step size of the positive (STEP
portions of the ramp are 32-bit values programmed into the 32-
bit rising and falling digital ramp step size registers (0x06 and
0x07). Program each of the step sizes as an unsigned integer
(the hardware automatically interprets STEP
value). The relationship between the 32-bit step size values and
actual units of frequency, phase, or amplitude depend on the digital
ramp destination bits. Calculate the actual frequency, phase, or
amplitude step size by substituting STEP
following equations as required:
AD9915
+
−
Frequency
Phase
Phase
Amplitude
∆
∆
t
t
=
=
Step
Step
f
f
SYSCLK
24
SYSCLK
24
Step
N
P
=
=
Step
π
45M
2
2
M
31
29
=
=






2
M
2
M
32
32






f
I
SYSCLK
FS
SYSCLK
P
. The timer establishes the
) and negative (STEP
N
or STEP
N
as a negative
P
for M in the
(radians)
(degrees)
N
) slope
Rev. A | Page 24 of 48
Note that the frequency units are the same as those used to
represent f
the same as those used to represent I
current of the DAC (mA, for example).
The phase and amplitude step size equations yield the average
step size. Although the step size accumulates with 32-bit precision,
the phase or amplitude destination exhibits only 16 bits or
12 bits, respectively. Therefore, at the destination, the actual
phase or amplitude step is the accumulated 32-bit value
truncated to 16 bits or 12 bits, respectively.
As described previously, the step interval is controlled by a
16-bit programmable timer. There are three events that can
cause this timer to be reloaded prior to its expiration. One event
occurs when the digital ramp enable bit transitions from cleared
to set, followed by an I/O update. A second event is a change of
state in the DRCTL pin. The third event is enabled using the load
LRR at I/O update bit (0x00[15]).
DRG Limit Control
The ramp accumulator is followed by limit control logic that
enforces an upper and lower boundary on the output of the
ramp generator. Under no circumstances does the output of the
DRG exceed the programmed limit values while the DRG is
enabled. The limits are set through the 64-bit digital ramp limit
register. Note that the upper limit value must be greater than the
lower limit value to ensure normal operation.
DRG Accumulator Clear
The ramp accumulator can be cleared (that is, reset to 0) under
program control. When the ramp accumulator is cleared, it forces
the DRG output to the lower limit programmed into the digital
ramp limit register.
With the limit control block embedded in the feedback path of the
accumulator, resetting the accumulator is equivalent to presetting it
to the lower limit value.
SYSCLK
(MHz, for example). The amplitude units are
FS
, the full-scale output
Data Sheet