AD9915 AD [Analog Devices], AD9915 Datasheet - Page 5

• Manufacturer Part Number: AD9915
• Description: 2.5 GSPS Direct Digital Synthesizer with 12-Bit DAC
• Manufacturer: AD [Analog Devices]

Data Sheet
AC SPECIFICATIONS
AVDD (1.8V) and DVDD (1.8V) = 1.8 V ± 5%, AVDD3 (3.3V) and DVDD_I/O (3.3V) = 3.3 V ± 5%, T
20 mA, external reference clock frequency = 2.5 GHz with reference clock (REF CLK) multiplier bypassed, unless otherwise noted.
Table 2.
Parameter
REF CLK INPUT
CLOCK DRIVERS
DAC OUTPUT CHARACTERISTICS
DIGITAL TIMING SPECIFICATIONS
REF CLK Multiplier Bypassed
System Clock (SYSCLK) PLL Enabled
SYNC_CLK Output Driver
SYNC_OUT Output Driver
Output Frequency Range (1
Output Resistance
Output Capacitance
Full-Scale Output Current
Gain Error
Output Offset
Voltage Compliance Range
Wideband SFDR
Narrow-Band SFDR
Time Required to Enter Power-Down
Time Required to Leave Power-Down
Minimum Master Reset time
Maximum DAC Calibration Time (t
Maximum PLL Calibration Time (t
Maximum Profile Toggle Rate
Frequency Range
497.5 MHz Output
Input Frequency Range
Duty Cycle
Minimum Differential Input Level
VCO Frequency Range
VCO Gain (K
Maximum PFD Rate
Frequency Range
Duty Cycle
Rise Time/Fall Time (20% to 80%)
Duty Cycle
Rise Time (20% to 80%)
Fall Time (20% to 80%)
Zone)
122.5 MHz Output
305.3 MHz Output
497.5 MHz Output
978.2 MHz Output
122.5 MHz Output
305.3 MHz Output
978.2 MHz Output
V
)
st
Nyquist
REF_CLK
CAL
)
)
Min
500
45
632
2400
45
33
0
−10
AVDD −
0.50
24
Typ
60
50
650
1350
1670
50
5
−67
−66
−59
−60
−95
−95
−95
−92
45
250
Rev. A | Page 5 of 48
Max
2500
55
2500
125
156
55
6.5
66
1250
20.48
+10
0.6
AVDD +
0.50
152
16
8
1
Unit
MHz
%
mV p-p
MHz
MHz/V
MHz
MHz
%
ps
MHz
%
ps
ps
MHz
Ω
pF
mA
% FS
μA
V
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
ns
ns
SYSCLK cycles
µs
ms
ms
SYNC_CLK period
Test Conditions/Comments
Input frequency range
Maximum f
Equivalent to 316 mV swing on each leg
10 pF load
CFR2 register, Bit 9 = 1
10 pF load
10 pF load
Single-ended (each pin internally terminated to
AVDD (3.3V))
Range depends on DAC R
See the Typical Performance Characteristics
section
0 MHz to 1250 MHz
0 MHz to 1250 MHz
0 MHz to 1250 MHz
0 MHz to 1250 MHz
See the Typical Performance Characteristics
section
±500 kHz
±500 kHz
±500 kHz
±500 kHz
Power-down mode loses DAC/PLL calibration
settings
Must recalibrate DAC/PLL
f
DAC Calibration Output section for formula
PFD rate = 25 MHz
PFD rate = 50 MHz
CAL
= f
SYSCLK
/384 USR0 register, Bit 6 = 0; see the
A
OUT
= 25°C, R
is 0.4 × f
SYSCLK
SET
SET
= 3.3 kΩ, I
resistor
AD9915
OUT
=