AD9915 AD [Analog Devices], AD9915 Datasheet - Page 23

• Manufacturer Part Number: AD9915
• Description: 2.5 GSPS Direct Digital Synthesizer with 12-Bit DAC
• Manufacturer: AD [Analog Devices]

Data Sheet
DIGITAL RAMP GENERATOR (DRG)
DRG Overview
To sweep phase, frequency, or amplitude from a defined start
point to a defined endpoint, a completely digital ramp generator
is included in the AD9915. The DRG makes use of eight control
register bits, three external pins, and five 32-bit registers (see
Figure 36).
The primary control for the DRG is the digital ramp enable bit
(0x01[19]). When disabled, the other DRG input controls are
ignored and the internal clocks are shut down to conserve power.
DIGITAL RAMP LOWER LIMIT REGISTER
DIGITAL RAMP UPPER LIMIT REGISTER
DIGITAL RAMP RATE REGISTER
FALLING DIGITAL RAMP STEP
RISING DIGITAL RAMP STEP
DIGITAL RAMP DESTINATION
LOAD LRR AT I/O_UPDATE
SIZE REGISTER
SIZE REGISTER
DIGITAL RAMP NO-DWELL
DIGITAL RAMP ENABLE
RAMP ACCUMULATOR
RAMP ACCUMULATOR
AUTOCLEAR DIGITAL
Figure 36. Digital Ramp Block Diagram
LOAD LRR AT I/O_UPDATE
CLEAR DIGITAL
NEGATIVE SLOPE RATE
DECREMENT STEP SIZE
INCREMENT STEP SIZE
POSITIVE SLOPE RATE
DDS CLOCK
DRHOLD
DRCTL
2
2
32
32
32
32
32
GENERATOR
63
DDS CLOCK
62
63
DIGITAL
CONTROL
RAMP
LOGIC
64
32
32
16
16
LOAD
0
1
0
1
65
32
Figure 37. Digital Ramp Generator Detail
TO DDS
SIGNAL
CONTROL
PARAMETER
32
16
LOAD
PRESET
DIGITAL
RAMP
TIMER
Rev. A | Page 23 of 48
Q
32
32
DIGITAL RAMP ACCUMULATOR
D
R
Q
ACCUMULATOR
The output of the DRG is a 32-bit unsigned data bus that can be
routed to any one of the three DDS signal control parameters, as
controlled by the two digital ramp destination bits in Control
Function Register 2 according to Table 9. The 32-bit output bus
is MSB-aligned with the 32-bit frequency parameter, the 16-bit
phase parameter, or the 12-bit amplitude parameter, as defined
by the destination bits. When the destination is phase or
amplitude, the unused LSBs are ignored.
Table 9. Digital Ramp Destination
Digital Ramp
Destination Bits
(CFR2[21:20])
00
01
1x
1
The ramp characteristics of the DRG are fully programmable. This
includes the upper and lower ramp limits, and independent control
of the step size and step rate for both the positive and negative slope
characteristics of the ramp. A detailed block diagram of the DRG is
shown in Figure 37.
The direction of the ramping function is controlled by the
DRCTL pin. Logic 0 on this pin causes the DRG to ramp
with a negative slope, whereas Logic 1 causes the DRG to ramp
with a positive slope.
The DRG also supports a hold feature controlled via the DRHOLD
pin. When this pin is set to Logic 1, the DRG is stalled at its last
state; otherwise, the DRG operates normally. The DDS signal
control parameters that are not the destination of the DRG are
taken from the active profile.
CONTROL
x = don’t care.
RESET
LOGIC
1
32
UPPER
LIMIT
LIMIT CONTROL
32
LOWER
LIMIT
CLEAR DIGI T AL RAMP ACCUMULATOR
AUTOCLEAR DIGI T AL RAMP ACC
NO-DWELL
CONTROL
DDS Signal
Control
Parameter
Frequency
Phase
Amplitude
32
2
NO DWELL
TO DDS
SIGNAL
CONTROL
PARAMETER
.
31:0
31:20
Bits Assigned to
DDS Parameter
31:18
AD9915