AD9915 AD [Analog Devices], AD9915 Datasheet - Page 34

• Manufacturer Part Number: AD9915
• Description: 2.5 GSPS Direct Digital Synthesizer with 12-Bit DAC
• Manufacturer: AD [Analog Devices]

MULTIPLE CHIP SYNCHRONIZATION
Multiple devices are synchronized when their clock states match
and they transition between states simultaneously. Clock
synchronization allows the user to asynchronously program
multiple devices but synchronously activate the programming
by applying a coincident I/O update to all devices. The function
of the synchronization logic in the
internal clock generator to a predefined state coincident with an
external synchronization signal applied to the SYNC_IN pin. If
all devices are forced to the same clock state in synchronization
with the same external signal, the devices are, by definition,
synchronized.
To use the multichip synchronization feature, two requirements
must be met. First, a synchronization signal must be provided
to the device. Second, 0x1B[6] must be set. The actual
synchronization process occurs as part of the DAC calibration,
as follows. When the DAC CAL enable bit is set in 0x03, the
device undergoes the first step of the calibration phase and then
pauses to allow the synchronization process to complete. It is
important to note that, if the synchronization signal is not
present and 0x1B[6] is set, the calibration does not successfully
complete. After the synchronization is finished, the DAC clock
calibration proceeds to completion. When employing the
multichip synchronization, the amount of time to complete the
DAC clock calibration increases by an amount of time equal to
16 cycles of the synchronization signal.
Figure 48 is a block diagram of the synchronization function.
The synchronization logic is divided into two independent
blocks: a SYNC_OUT generator and a SYNC_IN receiver. The
SYNC_OUT generator consists of a free running divider
clocked by the internal system clock, the same clock from which
all other internal clock signals are derived. The SYNC_OUT
generator block is activated via the SYNC_OUT enable bit in
the CFR2 register (0x01[9]). The SYNC out/in mux enable bit
(0x01[8]) is an output enable bit. Both bits must be in a logic
high state for the internal generator to be active at Pin 61. Either
bit turns off the output signal. However, if the SYNC_OUT
enable bit (0x01[9]) is cleared, the device takes the signal that is
present at Pin 62 and buffers it before driving it out on Pin 61.
For one
source with the remaining devices slaved to the master, set
the SYNC_OUT enable and SYNC out/in mux enable bits
(0x01[9:8]) = 0x03. Set the SYNC_OUT enable bit (0x01[9]) =
0x0 for the devices slaved to the master, whereas SYNC out/in
mux enable bit (0x01[8]) can be either set or cleared. The sync
generator produces a clock signal that appears at the SYNC_
OUT pin. This clock is delivered by a CMOS output driver and
exhibits a 67% duty cycle and has a fixed frequency given by
f
clock at the SYNC_OUT pins synchronizes with the rising edge
of the internal SYSCLK signal. Because the SYNC_OUT signal
is synchronized with the internal SYSCLK of the master device,
the master device SYSCLK serves as the reference timing source
AD9915
SYS
/384, where f
AD9915
SYS
in a group to function as a master timing
refers to the system clock frequency. The
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is to force the
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for all slave devices. The user can adjust the output delay of the
SYNC_OUT signal by programming the 3-bit SYNC_OUT
delay ADJ word in the USR0 register (0x1B[5:3]) via the serial
I/O port.
The sync receiver block is a CMOS input that accepts a periodic
clock signal, known as the SYNC_IN signal, at Pin 62 and
delivers it to the appropriate clock generation circuitry
requiring synchronization. If the
master timing device for multiple devices, the sync receiver
block can be used to buffer a signal from Pin 62 to Pin 61. The
user can delay the SYNC_IN signal by programming the 3-bit
input SYNC_IN delay ADJ word in the USR0 register
(0x1B[2:0]). Edge detection logic generates a sync pulse having
a duration of one SYSCLK cycle with a repetition rate equal to
the frequency of the signal applied to the SYNC_IN pin. The
sync pulse is generated as a result of sampling the rising edge of
the SYNC_IN signal with the rising edge of the local SYSCLK.
The sync pulse is routed to the internal clock generator, which
behaves as a presettable counter clocked at the SYSCLK rate.
The sync pulse presets the counter to a predefined state. The
predefined state is active for only a single SYSCLK cycle, after
which the clock generator resumes cycling through its state
sequence at the SYSCLK rate.
Multiple device synchronization is accomplished by providing
each
all the devices. This concept is shown in Figure 49, in which
three
operating as a master timing unit and the others as slave units.
The master device must have its SYNC_IN pin included as part
of the synchronization distribution and delay equalization
mechanism in order for it to be synchronized with the slave
units. The synchronization mechanism relies on the premise
that the REF_CLK signal appearing at each device is edge
aligned with all others as a result of the external REF_CLK
distribution system (see Figure 49).
SYNC_OUT
SYNC_CLK
REF_CLK
REF_CLK
SYNC_IN
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82
54
55
61
62
CFR2 [9]
with a SYNC_IN signal that is edge aligned across
Figure 48. Synchronization Block Diagram
devices are synchronized, with one device
GENERATOR
CIRCUITRY
SYNC OUT
REF CLK
RECEIVER
INPUT
SYNC IN
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SYSCLK
GENERATOR
is not enabled as a
INTERNAL
CLOCKS
Data Sheet
INTERNAL
CLOCKS