AD9915 AD [Analog Devices], AD9915 Datasheet - Page 22

• Manufacturer Part Number: AD9915
• Description: 2.5 GSPS Direct Digital Synthesizer with 12-Bit DAC
• Manufacturer: AD [Analog Devices]

PLL Charge Pump
The charge pump current (I
the VCO calibration process and feedback divider (N = 8 to
255) value stored in Feedback Divider N[7:0] in the CFR3
register (0x02[15:8]). To manually override the charge pump
current value, the manual I
must be set to Logic 1.
This provides the user with additional flexibility to optimize the
PLL performance. Table 7 lists the bit settings vs. the nominal
charge pump current.
Table 7. PLL Charge Pump Current
I
000
001
010
011
100
101
110
111
Table 8. N divider vs. Charge Pump Current
N Divider Range
8 to 15
16 to 23
24 to 35
36 to 43
44 to 55
56 to 63
64 to 79
80 to 100
PLL Loop Filter Components
The loop filter is mostly internal to the device, as shown in
Figure 34. The recommended external capacitor value is 560 pF.
Because C
adjust the loop bandwidth via the external capacitor value. The
better option is to adjust the charge pump current even though
it is a coarse adjustment.
For example, suppose the PLL is manually programmed such
that I
loop bandwidth of approximately 250 kHz.
AD9915
CP
Bits (CFR3[5:3])
CP
= 375 μA, K
P
and R
PZ
V
are integrated, it is not recommended to
= 60 MHz/V, and N = 50. This produces a
Charge Pump Current, I
125
250
375
500 (default)
625
750
875
1000
Recommended Charge Pump
Current, I
125
250
375
500
625
750
875
1000
CP
CP
selection bit in CFR3 (0x02[6])
) value is automatically chosen via
CP
(μA)
CP
(μA)
Rev. A | Page 22 of 48
PLL LOCK INDICATION
When the PLL is in use, the PLL lock bit (0x1B[24])provides an
active high indication that the PLL has locked to the REF CLK
input signal.
OUTPUT SHIFT KEYING (OSK)
The OSK function (see Figure 35) allows the user to control the
output signal amplitude of the DDS. The amplitude data
generated by the OSK block has priority over any other
functional block that is programmed to deliver amplitude data
to the DDS. Therefore, the OSK data source, when enabled,
overrides all other amplitude data sources.
The operation of the OSK function is governed by two CFR1
register bits, OSK enable (0x00[8]) and external OSK
enable(0x00[9]), the external OSK pin, the profile pins, and the
12 bits of amplitude scale factor found in one of eight profile
registers. The profile pins are used to select the profile register
containing the desired amplitude scale factor.
The primary control for the OSK block is the OSK enable bit
(0x00[8]). When the OSK function is disabled, the OSK input
controls and OSK pin are ignored.
The OSK pin functionality depends on the state of the external
OSK enable bit and the OSK enable bit. When both bits are set
to Logic 1 and the OSK pin is Logic 0, the output amplitude is
forced to 0; otherwise, if the OSK pin is Logic 1, the output
amplitude is set by the amplitude scale factor value in one of
eight profile registers depending on the profile pin selection.
PS0 PS1 PS2
25
26
PLL IN
27
SELECTED PROFILE
REGISTERS [27:16])
AMPLITUDE SCALE
0.22pF
FACTOR (1 OF 8
50pF
Figure 34. REF CLK PLL External Loop Filter
C
OSK ENABLE
OSK ENABLE
P
REFCLK PLL
EXTERNAL
59
Figure 35. OSK Block Diagram
PFD
REF
÷N
CP
12
58
LOOP_FILTER
R
CONTROLLER
C
DDS CLOCK
PZ
Z
= 560pF (RECOMMENDED)
VCO
(3.5kΩ)
OSK
OSK
66
12
Data Sheet
PLL OUT
PARAMETER
AMPLITUDE
CONTROL
TO DDS