AD9915 AD [Analog Devices], AD9915 Datasheet - Page 27

• Manufacturer Part Number: AD9915
• Description: 2.5 GSPS Direct Digital Synthesizer with 12-Bit DAC
• Manufacturer: AD [Analog Devices]

Data Sheet
DROVER Pin
The DROVER pin provides an external signal to indicate the status
of the DRG. Specifically, when the DRG output is at either of
the programmed limits, the DROVER pin is Logic 1; otherwise,
it is Logic 0. In the special case of both no-dwell bits set, the
DROVER pin pulses positive for two DDS clock cycles each
time the DRG output reaches either of the programmed limits.
Frequency Jumping Capability in DRG Mode
Another feature of the
predefined range of frequencies during a normal sweep. The
frequency jump enable bit in CFR2 (0x01[14]) enables this
functionality. When this bit is set, the sweeping logic monitors
the instantaneous frequency. When it reaches the frequency
point defined in the lower frequency jump register (0x09) on
the next accumulation cycle, instead of accumulating a delta
tuning word as in normal sweeping, it skips directly to the
frequency value set in the upper frequency jump register
(0x0A), and vice versa. Figure 40 shows how this feature works.
A second frequency jump can also be allowed if the frequency
jump registers are reprogrammed before the sweeping is
complete.
The following rules apply when this feature is enabled.
•
•
FREQUENCY
LOWER LIMIT
UPPER LIMIT
The frequency jump values must lie between the lower
limit and upper limit of the frequency sweep range.
The lower frequency jump register value must be lower
than that of the upper frequency jump register value.
0x0A
0x09
Figure 40. Frequency vs. Time
AD9915
allows the user to skip a
t
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POWER-DOWN CONTROL
The
three specific sections of the device. Power-down functionality
applies to the following:
•
•
•
A power-down of the digital core disables the ability to update
the serial/parallel I/O port. However, the digital power-down
bit (0x00[7]) can still be cleared to prevent the possibility of a
nonrecoverable state.
Software power-down is controlled via three independent power-
down bits in CFR1. Software control requires that the
EXT_PWR_DWN pin be forced to a Logic 0 state. In this case,
setting the desired power-down bits (0x00[7:5]) via the serial
I/O port powers down the associated functional block, whereas
clearing the bits restores the function.
Alternatively, all three functions can be simultaneously powered
down via external hardware control through the EXT_PWR_DWN
pin. When this pin is forced to Logic 1, all four circuit blocks are
powered down regardless of the state of the power-down bits;
that is, the independent power-down bits in CFR1 are ignored
and overridden when EXT_PWR_DWN is Logic 1.
Based on the state of the external power-down control bit, the
EXT_PWR_DWN pin produces either a full power-down or a
fast recovery power-down. The fast recovery power-down
mode maintains power to the DAC bias circuitry and the PLL,
VCO, and input clock circuitry. Although the fast recovery
power-down does not conserve as much power as the full
power-down, it allows the device to awaken very quickly from
the power-down state.
AD9915
Digital core
DAC
Input REF CLK clock circuitry
offers the ability to independently power down
AD9915