AD9915 AD [Analog Devices], AD9915 Datasheet - Page 33

• Manufacturer Part Number: AD9915
• Description: 2.5 GSPS Direct Digital Synthesizer with 12-Bit DAC
• Manufacturer: AD [Analog Devices]

Data Sheet
PARALLEL PROGRAMMING (8-/16-BIT)
The state of the external function pins (F0 to F3) determine the
type of interface used by the AD9915. Pin 28 to Pin 31 are
dedicated function pins. To enable the parallel mode interface
set Pin 28 to Pin 31 to logic low.
Parallel programming consists of eight address lines and either
eight or16 bidirectional data lines for read/write operations. The
logic state on Pin 22 determines the width of the data lines used. A
logic low on Pin 22 sets the data width to eight bits, and logic high
sets the data width to 16 bits. In addition, parallel mode has
dedicated write/read control inputs. If 16-bit mode is used, the
upper byte, Bits[15:8], goes to the addressed register and the
lower byte, Bits[7:0], goes to the adjacent lower address.
Parallel I/O operation allows write access to each byte of any
register in a single I/O operation. Readback capability for each
register is included to ease designing with the AD9915.
D[7:0] OR
D[7:0] OR
D[15:0]
D[15:0]
A[7:0]
A[7:0]
RD
WR
A1
D1
A1
D1
t
AHD
t
t
RDHIGH
WRHIGH
t
RDHOZ
t
ASU
t
ADV
Figure 47. Parallel Port Write Timing Diagram
Figure 46. Parallel Port Read Timing Diagram
t
RDLOV
t
t
WR
RDLOW
t
WRLOW
Rev. A | Page 33 of 48
t
DSU
A2
D2
A2
D2
Table 12. Parallel Port Read Timing (See Figure 46)
Parameter
t
t
t
t
t
t
Table 13. Parallel Port Write Timing (See Figure 47)
Parameter
t
t
t
t
t
t
t
ADV
AHD
RDLOV
RDHOZ
RDLOW
RDHIGH
ASU
DSU
AHD
DHD
WRLOW
WRHIGH
WR
t
AHD
t
DHD
Value
92
0
69
50
69
50
Value
1
3.8
0
0
2.1
3.8
10.5
Unit
ns max
ns min
ns max
ns max
ns max
ns max
Unit
ns
ns
ns
ns
ns
ns
ns
Test Conditions/Comments
Address to data valid time
Address hold time to RD signal
inactive
RD low to output valid
RD high to data three-state
RD signal minimum low time
RD signal minimum high time
Test Conditions / Comments
Address setup time to WR
signal active
Data setup time to WR signal
active
Address hold time to WR
signal inactive
Data hold time to WR signal
inactive
WR signal minimum low time
WR signal minimum high time
Minimum write time
A3
D3
A3
D3
AD9915