AD9915 AD [Analog Devices], AD9915 Datasheet - Page 30

• Manufacturer Part Number: AD9915
• Description: 2.5 GSPS Direct Digital Synthesizer with 12-Bit DAC
• Manufacturer: AD [Analog Devices]

Furthermore, to make use of amplitude control, the user must
be sure to program the OSK enable bit in the CFR1 register
(0x00[8]) to Logic 1.
The combination of the F[3:0] pins and Bits[31:0] provides the
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the user direct control of the DDS parameters (frequency,
phase, amplitude, or various combinations thereof).
Furthermore, the parallel port operates at a sample rate equal to
1/16 of the system sample clock. This allows for updates of the
DDS parameters at rates of up to 156 MSPS (assuming a
2.5 GHz system clock) allowing the
applications with wideband modulation requirements.
Be aware that the frequency, phase, and amplitude changes
applied at the parallel port travel to the DDS core over different
paths, experiencing different propagation times (latency).
Therefore, modulating more than one DDS parameter
necessitates setting the device’s matched latency enable bit in
the CFR2 register (0x01[15]), which equalizes the latency of
each DDS parameter as it propagates from the parallel port to
the DDS core. Note that high speed modulation requires a DAC
reconstruction filter with sufficient bandwidth to accommodate
the instantaneous time domain transitions.
Because direct access to the DDS parameters occurs via the
FTW, POW, and AMP registers, the IO_UPDATE pin (see
Figure 41) adds another layer of flexibility. To accommodate
this functionality, the
parallel port streaming enable (0x00[17]). When this bit is set
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with unprecedented modulation capability by allowing
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provides a register control bit,
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to accommodate
Rev. A | Page 30 of 48
to Logic 1, the parallel port operates without the need for an
I/O update. When this bit is Logic 0, however, the device
delivers the parallel port data to the appropriate registers (FTW,
POW, AMP), but not to the DDS core. Data does not transfer to
the DDS core until the user asserts the IO_UPDATE pin.
For example, suppose that an application requires frequency
and amplitude modulation with full 32-bit frequency resolution
and full 12-bit amplitude resolution. Note that none of the
F[3:0] pin combinations supports such modulation capability
directly. To circumvent this problem, set the parallel port
streaming enable bit (0x00[17]) to Logic 0. This allows for the
use of two direct mode cycles of the 32-pin parallel port, each
with a different function pin setting, without affecting the DDS
core until assertion of the IO_UPDATE pin. That is, during the
first direct mode cycle, set the function pins to F[3:0] = 0010,
which routes all 32 bits to the FTW register (frequency). On the
next direct mode cycle, set the function pins to F[3:0] = 0100,
which provides full 12-bit access to the AMP register (amplitude).
Be aware, however, this also provides access to the POW
register (phase); therefore, be sure keep the phase bits static.
Next, toggle the IO_UPDATE pin, which synchronously
transfers the new frequency and phase values from the FTW
and POW registers to the DDS core. This mode of operation
reduces the overall modulation rate by a factor of two because it
requires two separate operations on the parallel port. However,
this still allows for modulation sample rates as high as 78 MSPS.
Data Sheet