AD9915 AD [Analog Devices], AD9915 Datasheet - Page 41

• Manufacturer Part Number: AD9915
• Description: 2.5 GSPS Direct Digital Synthesizer with 12-Bit DAC
• Manufacturer: AD [Analog Devices]

Data Sheet
REGISTER BIT DESCRIPTIONS
The serial I/O port registers span an address range of 0 to 27
(0x00 to 0x1B in hexadecimal notation). This represents a total
of 28 individual serial registers. If programming in parallel mode,
the number of parallel registers increases to 112 individual
parallel registers. Additionally, the registers are assigned names
according to their functionality. In some cases, a register is
given a mnemonic descriptor. For example, the register at Serial
Address 0x00 is named Control Function Register 1 and is
assigned the mnemonic CFR1.
This section provides a detailed description of each bit in the
AD9915
a specific function, the entire group is considered a binary word
and is described in aggregate.
Control Function Register 1 (CFR1)—Address 0x00
Table 17. Bit Description for CFR1
Bits
[31:25]
24
[23:18]
17
16
15
14
13
12
11
10
register map. For cases in which a group of bits serves
Mnemonic
Open
VCO cal enable
Open
Parallel port streaming
enable
Enable sine output
Load LRR at I/O update
Autoclear digital ramp
accumulator
Autoclear phase accumulator
Clear digital ramp
accumulator
Clear phase accumulator
Open
Description
1 = initializes the auto internal PLL calibration. The calibration is required if the PLL is to
provide the internal system clock. Must first be reset to Logic 0 before another calibration can
be issued.
Open.
0 = the 32 bit parallel port needs an I/O update to activate or register any FTW, POW, or AMP
data presented to the 32-bit parallel port.
1 = the parallel port continuously samples data on the 32 input pins using SYNC_CLK and
multiplexes the value of FTW/POW/AMP accordingly, per the configuration of the F0 to F3
pins, without the need of an I/O update. Data must meet the setup and hold times of the
SYNC_CLK rising edge. If the function pins are used dynamically to alter data between
parameters, they must also meet the timing of the SYNC_CLK edge.
0 = cosine output of the DDS is selected.
1 = sine output of the DDS is selected (default).
Ineffective unless CFR2[19] = 1.
0 = normal operation of the digital ramp timer (default).
1 = interrupts the digital ramp timer operation to load a new linear ramp rate (LRR) value any
time I/O_UPDATE is asserted or a PS[2:0] change occurs.
0 = normal operation of the DRG accumulator (default).
1 = the digital ramp accumulator is reset for one cycle of the DDS clock (SYNC_CLK), after
which the accumulator automatically resumes normal operation. As long as this bit remains
set, the ramp accumulator is momentarily reset each time an I/O update is asserted or a PS[2:0]
change occurs. This bit is synchronized with either an I/O update or a PS[2:0] change and the
next rising edge of SYNC_CLK.
0 = normal operation of the DDS phase accumulator (default).
1 = synchronously resets the DDS phase accumulator anytime I/O_UPDATE is asserted or a
profile change occurs.
0 = normal operation of the digital ramp generator (default).
1 = asynchronous, static reset of the DRG accumulator. The ramp accumulator remains reset as
long as this bit remains set. This bit is synchronized with either an I/O update or a PS[2:0]
change and the next rising edge of SYNC_CLK.
0 = normal operation of the DDS phase accumulator (default).
1 = asynchronous, static reset of the DDS phase accumulator as long as this bit is set. This bit is
synchronized with either an I/O update or a PS[2:0] change and the next rising edge of
SYNC_CLK.
Open.
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This section is organized in sequential order of the serial addresses
of the registers. Each subheading includes the register name and
optional register mnemonic (in parentheses). Also given is the
serial address in hexadecimal format and the number of bytes
assigned to the register.
Following each subheading is a table containing the individual
bit descriptions for that particular register. The location of the
bit(s) in the register is indicated by a single number or a pair of
numbers separated by a colon; that is, a pair of numbers (A:B)
indicates a range of bits from the most significant (A) to the
least significant (B). For example, [5:2] implies Bit Position 5 to
Bit Position 2, inclusive, with Bit 0 identifying the LSB of the
register.
Unless otherwise stated, programmed bits are not transferred to
their internal destinations until the assertion of the I/O_UPDATE
pin or a profile pin change.
AD9915