AMD-K6 AMD [Advanced Micro Devices], AMD-K6 Datasheet - Page 5

no-image

AMD-K6

Manufacturer Part Number
AMD-K6
Description
AMD-K6 Processor
Manufacturer
AMD [Advanced Micro Devices]
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AMD-K6-2
Manufacturer:
AMD
Quantity:
20 000
Part Number:
AMD-K6-2/233AFR
Manufacturer:
AMD
Quantity:
20 000
Part Number:
AMD-K6-2/350AFR
Manufacturer:
AMD
Quantity:
20 000
Part Number:
AMD-K6-2/400AFR
Manufacturer:
SMC
Quantity:
4
Part Number:
AMD-K6-2/475ACK
Manufacturer:
CPGA
Quantity:
20 000
Part Number:
AMD-K6-2/533AFX
Manufacturer:
INTEL
Quantity:
37
Part Number:
AMD-K6-2/533AFX
Manufacturer:
AMD
Quantity:
20 000
20695H/0—March 1998
Contents
6
5.39
5.40
5.41
5.42
5.43
5.44
5.45
5.46
5.47
5.48
5.49
5.50
5.51
5.52
Bus Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
6.1
6.2
6.3
6.4
6.5
RESET (Reset) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
RSVD (Reserved) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
SCYC (Split Cycle) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
SMI# (System Management Interrupt) . . . . . . . . . . . . . . . . 111
SMIACT# (System Management Interrupt Active) . . . . . . 112
STPCLK# (Stop Clock) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
TCK (Test Clock) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
TDI (Test Data Input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
TDO (Test Data Output) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
TMS (Test Mode Select) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
TRST# (Test Reset) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
VCC2DET (V
W/R# (Write/Read) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
WB/WT# (Writeback or Writethrough) . . . . . . . . . . . . . . . . 116
Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Bus State Machine Diagram . . . . . . . . . . . . . . . . . . . . . . . . . 123
Idle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Data-NA# Requested. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Pipeline Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Pipeline Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Memory Reads and Writes . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Single-Transfer Memory Read and Write . . . . . . . . . . . . . . . 126
Misaligned Single-Transfer Memory Read and Write . . . . . 128
Burst Reads and Pipelined Burst Reads . . . . . . . . . . . . . . . . 130
Burst Writeback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
I/O Read and Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
Basic I/O Read and Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
Misaligned I/O Read and Write . . . . . . . . . . . . . . . . . . . . . . . 135
Inquire and Bus Arbitration Cycles . . . . . . . . . . . . . . . . . . . 136
Hold and Hold Acknowledge Cycle . . . . . . . . . . . . . . . . . . . . 136
HOLD-Initiated Inquire Hit to Shared or Exclusive
Line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
HOLD-Initiated Inquire Hit to Modified Line . . . . . . . . . . . 140
AHOLD-Initiated Inquire Miss. . . . . . . . . . . . . . . . . . . . . . . . 142
AHOLD-Initiated Inquire Hit to Shared or Exclusive
AHOLD-Initiated Inquire Hit to Modified Line . . . . . . . . . . 146
AHOLD Restriction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
Bus Backoff (BOFF#) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
Locked Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
Basic Locked Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
Locked Operation with BOFF# Intervention . . . . . . . . . . . . 154
Interrupt Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
Line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
Preliminary Information
CC2
Detect) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
AMD-K6
®
Processor Data Sheet
v

Related parts for AMD-K6