AMD-K6 AMD [Advanced Micro Devices], AMD-K6 Datasheet - Page 32

• Manufacturer Part Number: AMD-K6
• Description: AMD-K6 Processor
• Manufacturer: AMD [Advanced Micro Devices]

AMD-K6
Instruction Decode
Figure 4. AMD-K6
14
®
Processor Data Sheet
RISC86
On-Chip ROM
®
®
Sequencer
Processor Decode Logic
The AMD-K6 processor decode logic is designed to decode
multiple x86 instructions per clock (see Figure 4). The decode
logic accepts x86 instruction bytes and their predecode bits
from the instruction buffer, locates the actual instruction
boundaries, and generates RISC86 operations from these x86
instructions.
RISC86 operations are fixed-format internal instructions. Most
RISC86 operations execute in a single clock. RISC86 operations
are combined to perform every function of the x86 instruction
set. Some x86 instructions are decoded into as few as zero
RISC86 opcodes — for instance a NOP — or one RISC86
operation — a register-to-register add. More complex x86
instructions are decoded into several RISC86 operations.
Instruction Buffer
Vector Address
Preliminary Information
Internal Architecture
Short Decoder #1
Short Decoder #2
Long Decoder
Vector Decoder
4 RISC86 Operations
20695H/0—March 1998
Chapter 2