AMD-K6 AMD [Advanced Micro Devices], AMD-K6 Datasheet - Page 133

• Manufacturer Part Number: AMD-K6
• Description: AMD-K6 Processor
• Manufacturer: AMD [Advanced Micro Devices]

20695H/0—March 1998
5.49
Summary
Sampled
5.50
Summary
Driven
5.51
Summary
Driven and Floated
Chapter 5
TRST# (Test Reset)
W/R# (Write/Read)
VCC2DET (V
Input, Internal Pullup
The assertion of TRST# initializes the Test Access Port (TAP) by
resetting its state machine to the Test-Logic-Reset state. See
“Boundary-Scan Test Access Port (TAP)” on page 205 for details
regarding the operation of the TAP controller.
TRST# is a completely asynchronous input that does not
require a minimum setup and hold time relative to TCK. See
Table 54 on page 253 for the minimum pulse width requirement.
Output
VCC2DET is tied to V
logic that it must supply the specified processor core voltage to
the V
core, independent of the voltage supplied to the I/O buffers on
the V
VCC2DET always equals 0 and is never floated— even during
Tri-State Test mode.
Output
The processor drives W/R# to indicate whether it is performing
a write or a read cycle on the bus. In addition, W/R# is used to
define other bus cycles, including interrupt acknowledge and
special cycles (see Table 19 on page 119 for more details).
W/R# is driven off the same clock edge as ADS# and remains in
the same state until the clock edge on which NA# or the last
expected BRDY# of the cycle is sampled asserted. W/R# is
driven during memory cycles, I/O cycles, special bus cycles, and
interrupt acknowledge cycles.
W/R# is floated off the clock edge that BOFF# is sampled
asserted and off the clock edge that the processor asserts HLDA
in response to HOLD.
CC2
CC3
CC2
Detect)
pins.
pins. The V
Signal Descriptions
CC2
SS
(logic level 0) to indicate to the system
pins supply voltage to the processor
AMD-K6
®
Processor Data Sheet
115