AMD-K6 AMD [Advanced Micro Devices], AMD-K6 Datasheet - Page 31

• Manufacturer Part Number: AMD-K6
• Description: AMD-K6 Processor
• Manufacturer: AMD [Advanced Micro Devices]

20695H/0—March 1998
2.4
Instruction Fetch
Figure 3. The Instruction Buffer
Chapter 2
Return Address Stack
32-Kbyte Level-One
Instruction Fetch and Decode
Instruction Cache
Address Adders
Branch Target
16 x 16 Bytes
The processor can fetch up to 16 bytes per clock out of the
instruction cache or branch target cache. The fetched
information is placed into a 16-byte instruction buffer that
feeds directly into the decoders (see Figure 3). Fetching can
occur along a single execution stream with up to seven
outstanding branches taken.
The instruction fetch logic is capable of retrieving any 16
contiguous bytes of information within a 32-byte boundary.
There is no additional penalty when the 16 bytes of instructions
lie across a cache line boundary. The instruction bytes are
loaded into the instruction buffer as they are consumed by the
decoders. Although instructions can be consumed with byte
g ra nu l a r i t y, t h e i n s t r u c t i o n b u f f e r i s m a n a g e d o n a
memory-aligned word (2 bytes) organization. Therefore,
instructions are loaded and replaced with word granularity.
When a control transfer occurs— such as a JMP instruction—
set of 16 instruction bytes.
the entire instruction buffer is flushed and reloaded with a new
16 Bytes
Internal Architecture
16 Sets of Predecode Bits
Instruction Buffer
16 Instruction Bytes
Fetch Unit
plus
2:1
16 Bytes
AMD-K6
Branch-Target Cache
16 x 16 Bytes
®
Processor Data Sheet
13