AMD-K6 AMD [Advanced Micro Devices], AMD-K6 Datasheet - Page 185

• Manufacturer Part Number: AMD-K6
• Description: AMD-K6 Processor
• Manufacturer: AMD [Advanced Micro Devices]

20695H/0—March 1998
7
7.1
Chapter 7
Power-on Configuration and Initialization
BRDYC#
FLUSH#
Signals Sampled During the Falling Transition of RESET
BF[2:0]
On power-on the system logic must reset the AMD-K6 processor
by asserting the RESET signal. When the processor samples
RESET asserted, it immediately flushes and initializes all
internal resources and its internal state, including its pipelines
and caches, the floating-point state, the MMX state, and all
registers. Then the processor jumps to address FFFF_FFF0h to
start instruction execution.
FLUSH# is sampled on the falling transition of RESET to
determine if the processor begins normal instruction execution
or enters Tri-State Test mode. If FLUSH# is High during the
falling transition of RESET, the processor unconditionally runs
its Built-In Self Test (BIST), performs the normal reset
functions, then jumps to address FFFF_FFF0h to start
instruction execution. (See “Built-In Self-Test (BIST)” on page
203 for more details.) If FLUSH# is Low during the falling
transition of RESET, the processor enters Tri-State Test mode.
(See “Tri-State Test Mode” on page 204 and “FLUSH# (Cache
Flush)” on page 97 for more details.)
The in t er n a l op erat i n g f re q u e n cy o f t h e p roc e s so r is
determined by the state of the bus frequency signals BF[2:0]
when they are sampled during the falling transition of RESET.
The frequency of the CLK input signal is multiplied internally
by a ratio defined by BF[2:0]. (See “BF[2:0] (Bus Frequency)”
on page 86 for the processor-clock to bus-clock ratios.)
BRDYC# is sampled on the falling transition of RESET to
configure the drive strength of A[20:3], ADS#, HITM#, and
W/R#. If BRDYC# is Low during the fall of RESET, these
outputs are configured using higher drive strengths than the
standard strength. If BRDYC# is High during the fall of RESET,
the standard strength is selected. (See “BRDYC# (Burst Ready
Copy)” on page 89 for more details.)
Power-on Configuration and Initialization
AMD-K6
®
Processor Data Sheet
167