AMD-K6 AMD [Advanced Micro Devices], AMD-K6 Datasheet - Page 209

• Manufacturer Part Number: AMD-K6
• Description: AMD-K6 Processor
• Manufacturer: AMD [Advanced Micro Devices]

20695H/0—March 1998
9.2
9.3
Registers
Exceptions
FERR# and IGNNE#
Chapter 9
Multimedia Execution Unit
Floating-Point and MMX™ Instruction Compatibility
The multimedia execution unit of the AMD-K6 processor is
designed to accelerate the performance of software written
using the industry-standard MMX instructions. Applications
that can take advantage of the MMX instructions include
graphics, video and audio compression and decompression,
speech recognition, and telephony applications.
The multimedia execution unit can execute MMX instructions
in a single processor clock. To increase performance, the
processor is designed to simultaneously decode all MMX
instructions with most other instructions.
For more information on MMX instructions, refer to AMD-K6
Processor Multimedia Technology, order# 20726.
T h e e i g h t 6 4 -b i t M M X re g i s t e rs a re m a p p e d o n t h e
floating-point stack. This enables backward compatibility with
all existing software. For example, the register saving event
that is performed by operating systems during task switching
requires no changes to the operating system. The same support
provided in an operating system’s interrupt 7 handler (Device
Not Available) for saving and restoring the floating-point
registers also supports saving and restoring the MMX registers.
There are no new exceptions defined for supporting the MMX
instructions. All exceptions that occur while decoding or
executing an MMX instruction are handled in existing
exception handlers without modification.
MMX instructions do not generate floating-point exceptions.
However, if an unmasked floating-point exception is pending,
the processor asserts FERR# at the instruction boundary of the
next floating-point instruction, MMX instruction, or WAIT
instruction.
The sampling of IGNNE# asserted only affects processor
o p e ra t i o n d u r i n g t h e ex e c u t i o n o f a n e r ro r -s e n s i t ive
floating-point instruct ion, MMX inst ruct ion, or WAIT
instruction when the NE bit in CR0 is set to 0.
Floating-Point and Multimedia Execution Units
AMD-K6
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Processor Data Sheet
191
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