AMD-K6 AMD [Advanced Micro Devices], AMD-K6 Datasheet - Page 244

• Manufacturer Part Number: AMD-K6
• Description: AMD-K6 Processor
• Manufacturer: AMD [Advanced Micro Devices]

AMD-K6
12.3
Enter Stop Grant
Inquire State
Exit Stop Grant
Inquire State
12.4
Enter Stop Clock
State
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Processor Data Sheet
Stop Grant Inquire State
Stop Clock State
If INIT, INTR (if interrupts are enabled), FLUSH#, NMI, or
SMI# are sampled asserted in the Stop Grant state, the
processor latches the edge-sensitive signals (INIT, FLUSH#,
NMI, and SMI#), but otherwise does not exit the Stop Grant
state to service the interrupt. When the processor returns to the
Normal state due to sampling STPCLK# negated, any pending
interrupts are recognized after returning to the Normal state.
To ensure their recognition, all of the normal requirements for
these input signals apply within the Stop Grant state.
If RESET is sampled asserted in the Stop Grant state, the
processor immediately returns to the Normal state and the
reset process begins.
The Stop Grant Inquire state is entered from the Stop Grant
state or the Halt state when EADS# is sampled asserted during
an inquire cycle initiated by the system logic. The AMD-K6
processor responds to an inquire cycle in the same manner as in
the Normal state by driving HIT# and HITM#. If the inquire
cycle hits a modified data cache line, the processor performs a
writeback cycle.
Following the completion of any writeback, the processor
returns to the state from which it entered the Stop Grant
Inquire state.
If the CLK signal is stopped while the AMD-K6 processor is in
the Stop Grant state, the processor enters the Stop Clock state.
Because all internal clocks and the PLL are not running in the
Stop Clock s tat e, the St op Clock st at e represe nt s t he
minimum-power state of all clock control states. The CLK signal
must be held Low while it is stopped.
The Stop Clock state cannot be entered from the Halt state.
INTR is the only input signal that is allowed to change states
while the processor is in the Stop Clock state. However, INTR is
not sampled until the processor returns to the Stop Grant state.
Preliminary Information
Clock Control
20695H/0—March 1998
Chapter 12