AMD-K6 AMD [Advanced Micro Devices], AMD-K6 Datasheet - Page 204

• Manufacturer Part Number: AMD-K6
• Description: AMD-K6 Processor
• Manufacturer: AMD [Advanced Micro Devices]

AMD-K6
Cache Snooping
186
®
Processor Data Sheet
Table 32 shows the conditions under which snooping occurs in
the AMD-K6 processor and the resources that are snooped.
Table 32. Snoop Action
Notes:
Internal Snoop
Type of Event
Inquire Cycle
1. The processor’s response to an inquire cycle depends on the state of the INV input signal
2. If an internal snoop hits a modified line in the data cache, the line is written back and
3. If an internal snoop hits a line in the instruction cache, the instruction cache line is
–
and the state of the cache line as follows:
For the instruction cache, if INV is sampled negated, the line remains invalid or valid, but
if INV is sampled asserted, the line is invalidated.
For the data cache, if INV is sampled negated, valid lines remain in or transition to the
shared state, a modified data cache line is written back before the line is marked shared
(with HITM# asserted), and invalid lines remain invalid. For the data cache, if INV is
sampled asserted, the line is marked invalid. Modified lines are written back before
invalidation.
invalidated. Then the instruction cache performs a burst read from memory.
invalidated and the data-cache read or write is performed from memory.
Not applicable.
Preliminary Information
Cache Organization
Instruction
Cache
Cache
Data
Type of Access
System Logic
Write
Write
Read
Read
Read
Read
Miss
Miss
Miss
Hit
Hit
Hit
Instruction
Cache
yes
yes
yes
no
no
–
–
Snooping Action
1
3
3
20695H/0—March 1998
Data Cache
yes
yes
no
–
–
–
–
1
2
Chapter 8