AMD-K6 AMD [Advanced Micro Devices], AMD-K6 Datasheet - Page 129

• Manufacturer Part Number: AMD-K6
• Description: AMD-K6 Processor
• Manufacturer: AMD [Advanced Micro Devices]

20695H/0—March 1998
5.41
Summary
Driven and Floated
5.42
Summary
Chapter 5
SMI# (System Management Interrupt)
SCYC (Split Cycle)
Output
The processor asserts SCYC during misaligned, locked transfers
on the D[63:0] data bus. The processor generates additional bus
cycles to complete the transfer of misaligned data.
For purposes of bus cycles, the term aligned means:
SCYC is asserted off the same clock edge as ADS#, and negated
off the clock edge on which NA# or the last expected BRDY# of
the entire locked sequence is sampled asserted. SCYC is only
valid during locked memory cycles.
SCYC is floated off the clock edge that BOFF# is sampled
asserted and off the clock edge that the processor asserts HLDA
in response to HOLD.
Input, Internal Pullup
The assertion of SMI# causes the processor to enter System
Management Mode (SMM). Upon recognizing SMI#, the
processor performs the following actions, in the order shown:
1. Flushes its instruction pipelines
2. Completes all pending and in-progress bus cycles
3. Acknowledges the interrupt by asserting SMIACT# after
4. Saves the internal processor state in SMM memory
5. Disables interrupts by clearing the interrupt flag (IF) in
6. Jumps to the entry point of the SMM service routine at the
Any 1-byte transfers
2-byte and 4-byte transfers that lie within 4-byte address
boundaries
8-byte transfers that lie within 8-byte address boundaries
sampling EWBE# asserted
EFLAGS and disables NMI interrupts
SMM base physical address which defaults to 0003_8000h in
SMM memory
Signal Descriptions
AMD-K6
®
Processor Data Sheet
111