AMD-K6 AMD [Advanced Micro Devices], AMD-K6 Datasheet - Page 150

• Manufacturer Part Number: AMD-K6
• Description: AMD-K6 Processor
• Manufacturer: AMD [Advanced Micro Devices]

AMD-K6
Burst Writeback
132
®
Processor Data Sheet
Figure 48 on page 133 shows a burst read followed by a
writeback transaction. The AMD-K6 processor initiates
writebacks under the following conditions:
The processor drives writeback cycles during inquire or cache
flush cycles. The writeback shown in Figure 48 is caused by a
cache-line replacement. The processor completes the burst read
cycle that fills the cache line. Immediately following the burst
read cycle is the burst writeback cycle that represents the
modified line to be written back to memory. D[63:0] are driven
one clock edge after the clock edge on which ADS# is asserted
and are subsequently changed off the clock edge on which each
BRDY# assertion of the burst cycle is sampled.
Replacement—If a cache-line fill is initiated for a cache line
currently filled with valid entries, the processor uses a
least-recently-allocated (LRA) algorithm to select a line for
replacement. Before a replacement is made to a data cache
line that is in the modified state, the modified line is
scheduled to be written back to memory.
Internal Snoop—The processor snoops the data cache
whenever an instruction-cache line is read, and it snoops the
instruction cache whenever a data cache line is written. This
snooping is performed to determine whether the same
address is stored in both caches, a situation that is taken to
imply the occurrence of self-modifying code. If a snoop hits a
data cache line in the modified state, the line is written back
to memory before being invalidated.
WBINVD Instruction—When the processor executes a
WBINVD instruction, it writes back all modified lines in the
data cache and then invalidates all lines in both caches.
Cache
asserted, it executes a flush acknowledge special cycle and
writes back all modified lines in the data cache and then
invalidates all lines in both caches.
Preliminary Information
Flush—When
Bus Cycles
the
processor
samples
20695H/0—March 1998
FLUSH#
Chapter 6