AMD-K6 AMD [Advanced Micro Devices], AMD-K6 Datasheet - Page 224

• Manufacturer Part Number: AMD-K6
• Description: AMD-K6 Processor
• Manufacturer: AMD [Advanced Micro Devices]

AMD-K6
TAP Registers
206
®
Processor Data Sheet
Refer to “Electrical Data” on page 233 and “Signal Switching
Charac teristics” on page 241 to obtain t he electrical
specifications of the test signals.
The AMD-K6 processor provides an Instruction Register (IR)
a n d t h re e Te s t D a t a R e g i s t e rs ( T D R ) t o s u p p o r t t h e
boundary-scan architecture. The IR and one of the TDRs—the
Boundary-Scan Register (BSR)—consist of a shift register and
an output register. The shift register is loaded in parallel in the
Capture states. (See “TAP Controller State Machine” on page
212 for a description of the TAP controller states.) In addition,
the shift register is loaded and shifted serially in the Shift
states. The output register is loaded in parallel from its
corresponding shift register in the Update states.
Instruction Register (IR). The IR is a 5-bit register, without parity,
that determines which instruction to run and which test data
register to select. When the TAP controller enters the
Capture-IR state, the processor loads the following bits into the
IR shift register:
the state transitions of the TAP controller to occur. TCK can
be stopped in the logic 0 or 1 state.
TDI—The Test Data Input represents the input to the most
significant bit of all TAP registers, including the IR and all
test data registers. Test data and instructions are serially
shifted by one bit into their respective registers on the rising
edge of TCK.
TDO—The Test Data Output represents the output of the
least significant bit of all TAP registers, including the IR and
all test data registers. Test data and instructions are serially
shifted by one bit out of their respective registers on the
falling edge of TCK.
TMS—The Test Mode Select input specifies the test
function and sequence of state changes for boundary-scan
testing. If TMS is sampled High for five or more consecutive
clocks, the TAP controller enters its reset state.
TRST#—The Test Reset signal is an asynchronous reset that
unconditionally causes the TAP controller to enter its reset
state.
01b—Loaded into the two least significant bits, as specified
by the IEEE 1149.1 standard
000b—Loaded into the three most significant bits
Preliminary Information
Test and Debug
20695H/0—March 1998
Chapter 11