AMD-K6 AMD [Advanced Micro Devices], AMD-K6 Datasheet - Page 131

• Manufacturer Part Number: AMD-K6
• Description: AMD-K6 Processor
• Manufacturer: AMD [Advanced Micro Devices]

20695H/0—March 1998
5.44
Summary
Sampled
5.45
Summary
Sampled
Chapter 5
STPCLK# (Stop Clock)
TCK (Test Clock)
Input, Internal Pullup
The assertion of STPCLK# causes the processor to enter the
Stop Grant state, during which the processor’s internal clock is
stopped. From the Stop Grant state, the processor can
subsequently transition to the Stop Clock state, in which the
bus clock CLK is stopped. Upon recognizing STPCLK#, the
processor performs the following actions, in the order shown:
1. Flushes its instruction pipelines
2. Completes all pending and in-progress bus cycles
3. Acknowledges the STPCLK# assertion by executing a Stop
4. Stops its internal clock after BRDY# of the Stop Grant
5. Enters the Stop Clock state if the system logic stops the bus
See “Clock Control” on page 223 for more details regarding
clock control.
STPCLK# is sampled as a level-sensitive input on every clock
edge but is not recognized until the next instruction boundary.
System logic can drive the signal either synchronously or
asynchronously. If it is asserted asynchronously, it must be
asserted for a minimum pulse width of two clocks.
STPCLK# must remain asserted until recognized, which is
indicated by the completion of the Stop Grant special cycle.
Input, Internal Pullup
TCK is the clock for boundary-scan testing using the Test
Access Port (TAP). See “Boundary-Scan Test Access Port
(TAP)” on page 205 for details regarding the operation of the
TAP controller.
The processor always samples TCK, except while TRST# is
asserted.
Grant special bus cycle (see Table 19 on page 119)
special bus cycle is sampled asserted and after EWBE# is
sampled asserted
clock CLK (optional)
Signal Descriptions
AMD-K6
®
Processor Data Sheet
113