AMD-K6 AMD [Advanced Micro Devices], AMD-K6 Datasheet - Page 218

• Manufacturer Part Number: AMD-K6
• Description: AMD-K6 Processor
• Manufacturer: AMD [Advanced Micro Devices]

AMD-K6
10.7
200
®
Processor Data Sheet
I/O Trap Dword
Upon entry into SMM, the halt restart slot is defined as follows:
After entry into the SMI handler and before returning from
SMM, the halt restart slot can be written using the following
definition:
If the return from SMM takes the processor back to the Halt
state, the HLT instruction is not re-executed, but the Halt
special bus cycle is driven on the bus after the return.
If the assertion of SMI# is recognized during the execution of an
I/O instruction, the I/O trap dword at offset FFA4h in the SMM
state-save area contains information about the instruction. The
fields of the I/O trap dword are configured as follows:
Table 36 shows the format of the I/O trap dword.
Table 36. I/O Trap Dword Configuration
Address
I/O Port
31—16
Bits 15–1—Reserved
Bit 0—Point of entry to SMM:
1 = entered from Halt state
0 = not entered from Halt state
Bits 15–1—Reserved
Bit 0—Point of return when exiting from SMM:
1 = return to Halt state
0 = return to next instruction after the HLT instruction
Bits 31–16—I/O port address
Bits 15–4—Reserved
Bit 3—REP (repeat) string operation (1 = REP string, 0 = not
Bit 2—I/O string operation (1 = I/O string, 0 = not an I/O
Bit 1—Valid I/O instruction (1 = valid, 0 = invalid)
Bit 0—Input or output instruction (1 = INx, 0 = OUTx)
System Management Mode (SMM)
Reserved
Preliminary Information
a REP string)
string)
15—4
REP String
Operation
3
Operation
I/O String
2
Instruction
Valid I/O
1
20695H/0—March 1998
Chapter 10
Input or
Output
0