zl50411 Zarlink Semiconductor, zl50411 Datasheet - Page 83

• Manufacturer Part Number: zl50411
• Description: Managed 9-port Fast Ethernet Switch With Private Vlan
• Manufacturer: Zarlink Semiconductor

12.3.2.8
CPU Address: h0220+n (n = RMAC port number)
Accessed by CPU (R/W)
Only applicable if Private VLAN Edge feature is enable (FEN[1]=’1’).
NOTE: These registers overlap TRUNK6/7_HASHxy registers, thus, trunk groups 6 and 7 must be disabled
(TRUNK6=TRUNK7=0x00) if the PVLAN feature is enabled.
12.3.3
Trunk Group – Up to eight RMAC ports can be selected for each trunk group.
Bit [3]:
Bit [4]:
Bit [5]:
Bit [6]:
Bit [7]:
(Group 2 Address) Port Trunking Groups
Bits [7:0]
PVLAN_Pn – Per-Port Private VLAN Edge (Protected Ports)
Flooding control in secure mode
0: Enable - Learning disabled port will not receive any flooding packets (Default)
1: Disable
Support MAC address 0
0: MAC address 0 is not learned. (Default)
1: MAC address 0 is learned.
Disable IEEE multicast control frame (01-80-C2-00-00-00 to 01-80-C2-00-00-0F) to
CPU in managed mode. In unmanaged mode, frame is forwarded as multicast (except
PAUSE frame).
0: Frame is forwarded to CPU (Default)
1: Frame is forwarded as multicast (except PAUSE frame)
IP Multicast Enable
0: Disable (default)
1: Enable
In general, this bit is equal to ^FEN[4].
Enable logical port match in secure mode
0: Disable (Default)
1: Enable - When Well Known or User Define logical port force discard enabled, force
any IP packet with logical port number matching logical port numbers to CPU.
This means packet with destination MAC address 0 is forwarded as unknown
destination. It is subjected to unicast to multicast rate control.
Port 9,7-0 bit map of protected port n (Default 0x00)
Bits [7:0] represent ports 9,7-0, excluding the source port. For example:
For port 0, [7:0] represent ports 9,7..1
For port 1, [7:0] represent ports 9,7..2,0
For port 2, [7:0] represent ports 9,7..3,1..0
Zarlink Semiconductor Inc.
ZL50411
83
Data Sheet