zl50411 Zarlink Semiconductor, zl50411 Datasheet - Page 77

• Manufacturer Part Number: zl50411
• Description: Managed 9-port Fast Ethernet Switch With Private Vlan
• Manufacturer: Zarlink Semiconductor

12.3.1.4
I²C Address: h01E+n; CPU Address: h0081+2n (n = port number)
Accessed by CPU and I²C (R/W)
Port 0 – 7: (RMAC Ports)
Bit [1:0]:
Bit [2]:
Bits [4:3]:
Bit [5]:
Bit [6]:
Bit [7]:
Bit [3]:
Bits [6:4]
Bit [7]
ECR4Pn: Port n Control Register
Enable compress preamble
0: Send standard preamble (Default)
1: Only one byte preamble+SFD
Number of bytes removed from the Inter-Frame Gap (IFG). (Default 0x0)
Link Heart Beat Transmit (RMAC ports only)
0: Disable (Default)
1: Enable
Enable PHY Mode
00: MAC Mode (Default)
11: PHY Mode (Reverse MII/GPSI)
Only valid in MII and GPSI interface modes. In PHY mode, Mn_TXCLK &
Mn_RXCLK pins becomes outputs.
Internal loopback.
0: Disable (Default)
1: Enable
In this mode, the packet is looped back in the MAC layer before going out of the
chip. You must force linkup at full duplex as well.
External loopback is another level of system diagnostic which involves the PHY
device to loopback the packet.
Interface mode:
Frame loopback.
0: Disable frame from sending back to its source port. (Default)
1: Allow frame to send back to its source port
In a regular ethernet switch, a packet should never be receive and forwarded to
the same port. Setting the bit allows it to happen.
This is not the same as an ingress MAC loopback. The destination MAC address
has to be stored (learned) in the MCT and associated with the originating source
port. The frame loopback will only work for unicast packets.
Link Heart Beat Receive
0: Disable (Default). Also clears all MAC LHB status.
1: Enable
Soft reset.
0: Normal operation (Default)
1: Reset. Not self clearing.
00 - GPSI mode
01 - MII mode
10 - Reserved
11 - RMII mode (Default)
Zarlink Semiconductor Inc.
ZL50411
77
Data Sheet