zl50411 Zarlink Semiconductor, zl50411 Datasheet - Page 5

• Manufacturer Part Number: zl50411
• Description: Managed 9-port Fast Ethernet Switch With Private Vlan
• Manufacturer: Zarlink Semiconductor

January 2005
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June 2005
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December 2005
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April 2006
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Removed reference to direct register INDEX_REG1 (address 0x1) from SSI diagrams, as not applicable
Corrected ordering code to ZL50411GD”G”
Clarified that port mirroring is only available if the source & destination ports are in RMII mode
Updated PVMODE bit [5] to reflect the proper MAC address range: 01-80-C2-00-00-00~F
Clarified DATAOUT output can be open-drain or totem-pole based on debounce selection via bootstrap
TSTOUT[0]
Added power sequencing recommendation (1.7, “Power Sequencing“ on page 25)
Added Reverse MII/GPSI timing characteristics (13.4.10, “Reverse General Purpose Serial Interface
(RvGPSI)“ on page 139 and 13.4.11, “MII Management Data Interface (MDIO/MDC)“ on page 140)
Clarified that counter “DelayExceededDiscards” is not applicable for the ZL50411 (11.0, “Hardware Statistics
Counters“ on page 53)
Clarified that TRST signal should be externally tied to GND via weak resistor, as per JTAG standard (1.3,
“Ball Signal Descriptions“ on page 14)
Added more text to section 2.8, “JTAG“ on page 28
Clarified counter definitions (11.0, “Hardware Statistics Counters“ on page 53)
Added more explaination to VLAN ID Hashing feature: register FEN, bit [3]
Removed definition for SE_OPMODE bit[5] (ARP report control), as this feature was not implemented and
this bit was mistakenly left in the register definition.
Added Pb-free order code (ZL50411GDG2)
Added section on multicast MAC address learning/switching (5.11, “L2 Multicast Switching“ on page 44)
since it wasn’t really discussed in the DS
Clarified registers UCC, MCC & MCCTH
Renamed register UCC (now PCC), as name was misleading
Updated timing to CPU RvMII, as min. output delay should have been 0ns
Zarlink Semiconductor Inc.
ZL50411
5
Data Sheet