zl50411 Zarlink Semiconductor, zl50411 Datasheet - Page 2

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zl50411

Manufacturer Part Number
zl50411
Description
Managed 9-port Fast Ethernet Switch With Private Vlan
Manufacturer
Zarlink Semiconductor
Datasheet

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Part Number
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Part Number:
zl50411GDG2
Manufacturer:
ZARLINK
Quantity:
20 000
VLAN Support Features
Classification and Security
Traffic Management
Supports the following spanning standards
Supports Ethernet multicasting and broadcasting and flooding control
Supports the following VLAN standards
Supports both shared VLAN learning (SVL) and independent VLAN learning (IVL) of MAC addresses
Limited support for VLAN stacking (“Q-in-Q”)
Supports Private VLAN Edge (Protected Ports)
Search engine classification
Packet filtering and security
Two (2) transmission classes for FE ports and four (4) transmission classes for uplink port
Scheduling using weighted fair queuing (WFQ) or strict priority (SP) discipline
At egress, per-queue weighted random early discard (WRED) with 2 drop precedence levels
For FE ports, supports ingress and egress rate control
Output traffic regulation per class available on uplink port
Fully supports Differentiated Services' Expedited and Assured Forwarding (EF and AF) per-hop behaviours
Intelligent buffer management
Failover Features
Supports concentration mode
IEEE 802.1D spanning tree
IEEE 802.1w rapid spanning tree
port-based VLAN
IEEE 802.1Q tag-based VLAN, up to 4 K VLANs
Classifies packets based on single field
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Assigns a transmission priority and drop precedence
Static address filtering for source and/or destination MAC addresses
Static MAC address not subject to aging
Secure mode freezes MAC address learning (each port may independently use this mode)
IEEE 802.1x access control
Port-based priority: VLAN priority in a tagged frame can be overwritten by the priority of port VLAN ID
Configurable WRED thresholds
Bandwidth rationing, Bandwidth on demand, SLA (Service Level Agreement)
Granularity of rate regulation to 16 Kbps
Ingress rate regulated using WRED, with 2 drop precedence levels, or flow control
Achieves high buffer utilization while ensuring fairness among traffic classes and ports
Buffer reservations per class and per source port
Rapid link failure detection using hardware-generated heartbeat packets
link failover in less than 50 ms
Source and destination L4 logical ports, or
TOS/DS, or
VLAN (IEEE 802.1p), or
Physical port
Zarlink Semiconductor Inc.
ZL50411
2
Data Sheet

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