zl50411 Zarlink Semiconductor, zl50411 Datasheet - Page 48

• Manufacturer Part Number: zl50411
• Description: Managed 9-port Fast Ethernet Switch With Private Vlan
• Manufacturer: Zarlink Semiconductor

In addition, there is a shared pool, which can store any type of frame. The frame engine allocates the frames first in
the three priority sections. When the priority section is full or the packet has priority 1 or 0, the frame is allocated in
the shared pool. Once the shared pool is full the frames are allocated in the section reserved for the source port.
The following registers define the size of each section of the Frame data Buffer:
See Buffer Allocation application note, ZLAN-47, for more information.
7.6.1
As already discussed, the WRED mechanism may drop frames on output queue status. In addition to these
reasons for dropping, we also drop frames when global buffer space becomes scarce. The function of buffer
management is to make sure that such dropping causes as little blocking as possible.
If a received frame is dispatched to the P0 (“best effort”) queue, the buffer management will check on the overall
buffer situation plus the output queue status to decide the frame drop condition. If the source port has not enough
buffer for it, the frame will be dropped. If the output queue reaches PCC (packet congest control) and the shared
buffer has run out, the frame may be dropped by RED (at B%). If the output queue reaches PCC and the source
port reservation is lower than the buffer low threshold, the frame will be dropped.
For multicast frames, global thresholds are used to manage scarce resources. When a multicast frame is received,
the buffer management will check on the overall buffer situation. If total multicast resources reaches MCCTH
(multicast congest control threshold), the frame may be dropped by RED (at B%). If total multicast resources
reaches MCC, the frame will be dropped.
All the 100% dropping functions are disabled if the source port is flow control capable, however, RED (at B%) will
still be applied.
Per Source Port
-
-
-
-
-
-
-
Reservation
Reservation
PR100_N - Port Reservation for RMAC Ports
PR100_CPU - Port Reservation for CPU Port
PRM - Port Reservation for MMAC Port
SFCB - Share FCB Size
C1RS - Class 1 Reserve Size (priority 2 & 3)
C2RS - Class 2 Reserve Size (priority 4 & 5)
C3RS - Class 3 Reserve Size (priority 6 & 7)
Per Class
Dropping When Buffers Are Scarce
R
R
p0
pri1
Figure 12 - Buffer Partition Scheme
R
p1
R
Zarlink Semiconductor Inc.
pri2
R
ZL50411
p2
48
R
R
pri3
Temporary reservation
p3
R
p4
R
p5
Shared Pool S
R
p6
R
p7
(CPU)
R
p8
Data Sheet
R
p9