zl50411 Zarlink Semiconductor, zl50411 Datasheet - Page 107

• Manufacturer Part Number: zl50411
• Description: Managed 9-port Fast Ethernet Switch With Private Vlan
• Manufacturer: Zarlink Semiconductor

12.3.7.2
I²C Address: h0BD; CPU Address: h0601
Accessed by CPU and I²C (R/W)
12.3.7.3
I²C Address: h0BE; CPU Address: h0602
Accessed by CPU and I²C (R/W)
Bits [3:0]:
Bits [7:4]:
Bit [0]:
Bit [1]:
Bit [2]:
Bit [3]:
MII_OP1 – MII Register Option 1
FEN – Feature Enable Register
Duplex bit location in vendor specified register
Speed bit location in vendor specified register
(Default 00)
Statistic Counter
0 – Disable (Default)
1 – Enable (all ports)
When statistic counter is enable, an interrupt control frame is generated to
the CPU, every time a counter wraps around. This feature requires an
external CPU.
Private VLAN Edge Support
0: Disable (default)
1: Enable
If this feature is enabled, use registers PVLAN_Pn to set up the egress
protected port map. This feature is only applicable in tagged-based VLAN
mode (PVMODE[0]=’1’). In port-based VLAN mode (PVMODE[0]=’0’), this bit
must be 0.
See Private VLAN Edge application note, ZLAN-130, for more information.
Support DS EF Code.
0 – Disable (Default)
1 – Enable (all ports)
When 101110 is detected in DS field (TOS[7:2]), the frame priority is set for
110 and drop is set for 0.
Enable VLAN ID hashing
0 – Disable (Default)
1 – Enable
If this is enabled, the VLAN ID will be used along with the MAC address when
determining the HASH index for learning/searching. This is to allow
Independent VLAN Learning (IVL).
This feature is only applicable in tagged-based VLAN mode
(PVMODE[0]=’1’). In port-based VLAN mode (PVMODE[0]=’0’), this bit must
be ‘0’.
Zarlink Semiconductor Inc.
ZL50411
107
Data Sheet