zl50411 Zarlink Semiconductor, zl50411 Datasheet - Page 125

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zl50411

Manufacturer Part Number
zl50411
Description
Managed 9-port Fast Ethernet Switch With Private Vlan
Manufacturer
Zarlink Semiconductor
Datasheet

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12.3.11
12.3.11.1
CPU Address: h0F00
Accessed by CPU (R/W)
(Group F Address) CPU Access Group
Bit [0]:
Bit [1]:
Bit [2]:
Bit [3]:
Bit [4]:
Bits [7:5]:
GCR - Global Control Register
Store configuration (Default = 0)
Write ‘1’ followed by ‘0’ to store configuration into external EEPROM
Store configuration and reset (Default = 0)
Write ‘1’ to store configuration into external EEPROM and reset chip
Start BIST (Default = 0)
Write ‘1’ followed by ‘0’ to start the device’s built-in self-test. The result is
found in the DCR register.
Soft Reset (Default = 0)
Write ‘1’ to reset chip
Initialization Completed (Default = 0)
This bit is reserved in unmanaged mode.
In managed mode, the CPU writes this bit with ‘1’ to indicate initialization is
completed and ready to forward packets. The ‘0' to '1' transition will toggle
TSTOUT[2] from low to high.
Reserved
Zarlink Semiconductor Inc.
ZL50411
125
Data Sheet

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