zl50411 Zarlink Semiconductor, zl50411 Datasheet - Page 53

• Manufacturer Part Number: zl50411
• Description: Managed 9-port Fast Ethernet Switch With Private Vlan
• Manufacturer: Zarlink Semiconductor

10.1.2
M_CLK is a 50 MHz clock used for the RMAC ports (ports 0-7) and CPU port (port 8).
If none of the RMAC ports are configured in RMII mode or Reverse MII mode, a different clock frequency can be
applied to M_CLK, as long as it's less than 50 MHz. In this case, register USD must be set to provide an internal
1usec timing.
10.1.3
REF_CLK is a reference clock required for the MMAC port (port 9).
If the device is in a 9 port 10/100 configuration only, REF_CLK can be a lower frequency clock and can be
connected to M_CLK to reduce the number of clock sources.
If port 9 is not being used, REF_CLK can be left unconnected.
10.1.4
TCK is a clock used for the JTAG port. The frequency on this clock can vary. Refer to “JTAG (IEEE 1149.1-2001)”
on page 141 for the frequency range.
10.2
10.2.1
MDC is used for the MII Management Interface and clocks data on MDIO. It is generated by the device from
M_CLK and is equal to 500 kHz (M_CLK/100). If a different speed clock other than 50 MHz is used on M_CLK, the
USD register must be programmed to reset MDC.
10.2.2
SCL is used for the I2C interface and clocks data on SDA. It is generated by the device from M_CLK and is equal to
50kHz (M_CLK/1000). If a different speed clock other than 50 MHz is used on M_CLK, the USD register must be
programmed to reset SCL.
10.2.3
If the RMAC ports are configured in Reverse MII mode, TXCLK and RXCLK are generated from M_CLK and are
equal to M_CLK/2 for 100 M mode or M_CLK/20 for 10M mode. M_CLK needs to be a 50 MHz clock in this mode.
If the RMAC ports are configured in Reverse GPSI mode, TXCLK and RXCLK are generated from M_CLK and are
equal to M_CLK/2 for 10 M mode. M_CLK needs to be a 20 MHz clock in this mode and USD must be programmed
accordingly.
For the CPU port in serial+MII mode, TXCLK and RXCLK are generated from M_CLK and are equal to M_CLK/2 for
100 M mode or M_CLK/20 for 10 M mode. M_CLK needs to be a 50 MHz clock in this mode.
If the MMAC port is configured in Reverse MII mode, RXCLK is generated from REF_CLK and is equal to
REF_CLK/2 for 100 M mode (no support for 10M Reverse MII mode). REF_CLK needs to be a 50 MHz clock in this
mode.
11.0
11.1
ZL50411 hardware provides a full set of statistics counters for each Ethernet port. The CPU accesses these
counters through the CPU interface. All hardware counters are rollover counters. When a counter rolls over, the
CPU is interrupted, so that long-term statistics may be kept. The MAC detects all statistics, except for the filtering
Clock Generation
Hardware Statistics Counters List
Hardware Statistics Counters
RMAC Reference Clock (M_CLK) Speed Requirement
SCL
MMAC Reference Clock (REF_CLK) Speed Requirement
JTAG Test Clock (TCK) Speed Requirements
MDC
Ethernet Interface Clocks
Zarlink Semiconductor Inc.
ZL50411
53
Data Sheet