zl50411 Zarlink Semiconductor, zl50411 Datasheet - Page 26

• Manufacturer Part Number: zl50411
• Description: Managed 9-port Fast Ethernet Switch With Private Vlan
• Manufacturer: Zarlink Semiconductor

2.1
Two Megabit of internal memory is provided for ethernet Frame Data Buffering (FDB), storing of MAC Control Table
database (MCT), and the Network Management (NM) Database statistics counters and MIB.
The MCT is used for storing MAC addresses and their physical port number. The FDB is used for storing the
received frame data contents. The contents are stored in this memory until it is ready to be transmitted to the
egress port.
A memory arbiter is used to arbitrary the memory access requests from various sources. A Built In Self Test (BIST)
is used to detect any error in the memory array when the device is powered up. The BIST can also be requested by
the writing to the GCR register.
2.2
2.2.1
The RMII Media Access Control (RMAC) module provides the necessary buffers and control interface between the
Frame Engine (FE) and the external physical device (PHY). It has five interfaces: MII, RMII, GPSI (only for 10M),
Reverse MII, or Reverse GPSI (only for 10M).
The RMAC of the ZL50411 device meets the IEEE 802.3 specification. It is able to operate in either Half or Full
Duplex mode with a back pressure/flow control mechanism. In addition, it will automatically retransmit upon
collision for up to 16 total transmissions.
These eight ports are denoted as ports 0 to 7. The PHY addresses for the PHY devices connected to the 8 RMAC
ports has to be from 08h (port 0) to 0Fh (port 7).
2.2.1.1
The RMAC ethernet port can function in GPSI (7WS) mode. In this mode, the TXD[0], RXD[0] serve as TX data, RX
data and respectively. The link and duplex of the port can be controlled by programming the ECR1Pn register. Only
port-based VLAN is supported with GPSI interface.
2.2.2
The CPU Media Access Control (CMAC) module provides the necessary buffers and control interface between the
Frame Engine (FE) and the external CPU device. It support either a Reverse MII interface, providing the necessary
interface TX and RX clocks to the CPU, or a register access mechanism via the 8/16-bit or serial interface.
Using the MII interface, the CMAC of the ZL50411 device meets the IEEE 802.3 specification. It is able to operate in
either Half or Full Duplex mode with a back pressure/flow control mechanism. In addition, it will automatically
retransmit upon collision for up to 16 total transmissions.
This port is denoted as port 8.
2.2.3
The MII Media Access Control (MMAC) module provides the necessary buffers and control interface between the
Frame Engine (FE) and the external physical device (PHY). The MMAC implements an MII interface.
The MMAC of the ZL50411 device meets the IEEE 802.3 specification. It is able to operate in 10 M/100 M either
Half or Full Duplex mode with a back pressure/flow control mechanism. Furthermore, it will automatically retransmit
upon collision for up to 16 total transmissions.
This port is denoted as port 9. The PHY address for the PHY device connected to the MMAC port has to be 10h.
Internal Memory
MAC Modules
RMII MAC Module (RMAC)
CPU MAC Module (CMAC)
MII MAC Module (MMAC)
GPSI (7WS) Interface
Zarlink Semiconductor Inc.
ZL50411
26
Data Sheet