zl50411 Zarlink Semiconductor, zl50411 Datasheet - Page 4

• Manufacturer Part Number: zl50411
• Description: Managed 9-port Fast Ethernet Switch With Private Vlan
• Manufacturer: Zarlink Semiconductor

Changes Summary
July 2003
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November 2003
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February 2004
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August 2004
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November 2004
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Initial Release
Clarified IP Multicast support is up to 4K groups, as it wasn’t mentioned in the data sheets
Updated Ball Signal Description Table (1.3, “Ball Signal Descriptions“ on page 14):
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Updated 1.4, “Signal Mapping and Internal pull-up/Down Configuration“ on page 19 to indicate operation of
the internal pull-up/down resistors in different modes
Clarified 10.1.3, “MMAC Reference Clock (REF_CLK) Speed Requirement“ on page 53 on usage of
REF_CLK
Clarified PVMODE register bit description for bits [2] & [5]
Updated ECR4Pn register description as port 9 (uplink) operates differently than the RMAC ports for MII
bi-directional clocking (bits [1:0])
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Added Maximum Junction Temperature to 13.1, “Absolute Maximum Ratings“ on page 128
Updated I/O voltage levels to use TTL spec values rather than % of Vcc (13.2, “DC Electrical
Characteristics“ on page 128)
Added the following to the Feature List:
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Added section on PHY addresses (2.2.4, “PHY Addresses“ on page 27)
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Fixed error in DS on sending Ethernet Frames via 8/16-bit or serial interface.
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Added more cross-references to available AppNotes
Added section on Stacked VLAN (Q-in-Q) (5.9.3, “VLAN Stacking (Q-in-Q)“ on page 42) and IP Multicast
Switching (5.10, “IP Multicast Switching“ on page 43) since they weren’t really discussed in the DS
Added more clock descriptions to 10.0, “Clocks“ on page 52
INT_MASK and INTP_MASK registers should state that the default register value is 0x00
Added section Changes Summary to document
Added section on SCL clock generation (10.2.2, “SCL“ on page 53)
Interrupt Register was incorrectly identified as read only, should be read/write
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Updated CPU timing diagrams to clarify timing (13.4, “AC Characteristics and Timing“ on page 130)
Added section 1.6, “Default Switch Configuration and Initialization Sequence“ on page 23
Added Private VLAN Edge (protected ports), force VLAN tag out, and unknown IP Multicast filtering support
Updated CPU timing diagrams to clarify P_A timing (13.4, “AC Characteristics and Timing“ on page 130)
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C address mapping was corrected for QOSCn registers
clarified the ball signal I/O description for Mn_TXCLK & Mn_RXCLK showing these signals are either
inputs OR outputs
clarified that M9_MTXCLK is an input only
4 K jumbo frames
IEEE 802.3ad support
Reverse MII/GPSI
Clarified that they are hard-coded
The Status Bytes is sent before the frame, for both Tx and Rx
Clarified that only bit [7] is not self-clearing
Zarlink Semiconductor Inc.
ZL50411
4
Data Sheet