zl50411 Zarlink Semiconductor, zl50411 Datasheet - Page 28

• Manufacturer Part Number: zl50411
• Description: Managed 9-port Fast Ethernet Switch With Private Vlan
• Manufacturer: Zarlink Semiconductor

See Programming Timeout Reset application note, ZLAN-41, for more information.
2.8
An IEEE1149.1 compliant test interface is provided for boundary scan. The JTAG interface, collectively known as a
Test Access Port, or TAP, uses the following signals to support the operation of boundary scan:
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2.8.1
There are two types of registers associated with boundary scan. Each compliant device has one instruction register
and two or more data registers.
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2.8.2
The TAP controller, a state machine whose transitions are controlled by the TMS signal, controls the behaviour of
the JTAG system. For more detail on each state, refer to the IEEE 1149.1 Standard JTAG document.
2.8.3
The IEEE 1149.1 standard defines a set of instructions that must be available for a device to be considered
compliant. These instructions are:
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TCK – the TCK or ‘test clock’ synchronizes the internal state machine operations
TMS – the TMS or ‘test mode state’ is sampled at the rising edge of TCK to determine the next state
TDI – the TDI or ‘test data in’ represents the data shifted into the device’s test or programming logic. It is
sampled at the rising edge of TCK when the internal state machine is in the correct state
TDO – the TDO or ‘test data out’ represents the data shifted out of the device’s test or programming logic
and is valid on the falling edge of TCK when the internal state machine is in the correct state
TRST – the TRST or ‘test reset’ is an optional pin which, when available, can reset the TAP controller’s state
machine
Instruction Register – the instruction register holds the current instruction. Its content is used by the TAP
controller to decide what to do with signals that are received. Most commonly, the content of the instruction
register will define to which of the data registers signals should be passed.
Data Registers – there are three primary data registers, the Boundary Scan Register (BSR), the BYPASS
register and the IDCODES register. Other data registers may be present, but they are not required as part of
the JTAG standard.
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BYPASS – the BYPASS instruction causes the TDI and TDO lines to be connected via a single-bit
pass-through register (the BYPASS register). This instruction allows the testing of other devices in the JTAG
chain without any unnecessary overhead.
EXTEST – the EXTEST instruction causes the TDI and TDO to be connected to the Boundary Scan Register
(BSR). The device’s pin states are sampled with the ‘capture dr’ JTAG state and new values are shifted into
the BSR with the ‘shift dr’ state; these values are then applied to the pins of the device using the ‘update dr’
state.
SAMPLE/PRELOAD – the SAMPLE/PRELOAD instruction causes the TDI and TDO to be connected to the
BSR. However, the device is left in its normal functional mode. During this instruction, the BSR can be
accessed by a data scan operation to take a sample of the functional data entering and leaving the device.
The instruction is also used to preload test data into the BSR prior to loading an EXTEST instruction.
JTAG
BSR – this is the main testing data register. It is used to move data to and from the ‘pins’ on a device.
BYPASS – this is a single-bit register that passes information from TDI to TDO. It allows other devices in
a circuit to be tested with minimal overhead.
IDCODES – this register contains the ID code and revision number for the device. This information allows
the device to be linked to its Boundary Scan Description Language (BSDL) file. The file contains details of
the Boundary Scan configuration for the device.
Registers
Test Access Port (TAP) Controller
Boundary Scan Instructions
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ZL50411
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Data Sheet