zl50411 Zarlink Semiconductor, zl50411 Datasheet - Page 35

• Manufacturer Part Number: zl50411
• Description: Managed 9-port Fast Ethernet Switch With Private Vlan
• Manufacturer: Zarlink Semiconductor

acknowledgment style of protocol. The master IC generates the timing signals and terminates data transfer. Figure
7 depicts the data transfer format. The slave address is the memory address of the EEPROM. Refer to “ZL50411
Register Description” on page 62 for I²C address for each register.
3.2.1
Generated by the master (in our case, the ZL50411). The bus is considered to be busy after the Start condition is
generated. The Start condition occurs if while the SCL line is High, there is a High-to-Low transition of the SDA line.
Other than in the Start condition (and Stop condition), the data on the SDA line must be stable during the High
period of SCL. The High or Low state of SDA can only change when SCL is Low. In addition, when the I²C bus is
free, both lines are High.
3.2.2
The first byte after the Start condition determines which slave the master will select. The slave in our case is the
EEPROM. The first seven bits of the first data byte make up the slave address.
3.2.3
The eighth bit in the first byte after the Start condition determines the direction (R/W) of the message. A master
transmitter sets this bit to W; a master receiver sets this bit to R.
3.2.4
Like all clock pulses, the acknowledgment-related clock pulse is generated by the master. However, the transmitter
releases the SDA line (High) during the acknowledgment clock pulse. Furthermore, the receiver must pull-down the
SDA line during the acknowledge pulse so that it remains stable Low during the High period of this clock pulse. An
acknowledgment pulse follows every byte transfer.
If a slave receiver does not acknowledge after any byte, then the master generates a Stop condition and aborts the
transfer.
If a master receiver does not acknowledge after any byte, then the slave transmitter must release the SDA line to let
the master generate the Stop condition.
3.2.5
After the first byte containing the address, all bytes that follow are data bytes. Each byte must be followed by an
acknowledge bit. Data is transferred MSB first.
3.2.6
Generated by the master. The bus is considered to be free after the Stop condition is generated. The Stop condition
occurs if while the SCL line is High, there is a Low-to-High transition of the SDA line.
3.3
The synchronous serial interface (SSI) serves the function of configuring the ZL50411 not at boot time but via a PC.
The PC serves as master and the ZL50411 serves as slave. The protocol for the synchronous serial interface is
nearly identical to the I²C protocol. The main difference is that there is no acknowledgment bit after each byte of
data transferred. Debounce logic on the clock signal (STROBE) can be turned off to speedup command time.
START
Synchronous Serial Interface
Start Condition
Address
Data Direction
Acknowledgment
Data
Stop Condition
SLAVE ADDRESS
Figure 7 - Data Transfer Format for I²C Interface
R/W
ACK
Zarlink Semiconductor Inc.
DATA 1 (8bits)
ZL50411
35
ACK
DATA 2
ACK
DATA M
ACK
Data Sheet
STOP