zl50411 Zarlink Semiconductor, zl50411 Datasheet - Page 79

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zl50411

Manufacturer Part Number
zl50411
Description
Managed 9-port Fast Ethernet Switch With Private Vlan
Manufacturer
Zarlink Semiconductor
Datasheet

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12.3.1.5
CPU Address: h0036
Accessed by CPU (R/W)
12.3.1.6
CPU Address: h0037
Accessed by CPU (R/W)
12.3.2
12.3.2.1
I²C Address: h028; CPU Address: h0100
Accessed by CPU and I²C (R/W)
Bits [2:0]:
Bits [7:3]:
Bits [6:0]:
Bit [7]:
Bits [7:0]:
(Group 1 Address) VLAN Group
Bit [5]:
Bit [6]:
Bit [7]:
BUF_LIMIT – Frame Buffer Limit
FCC – Flow Control Grant Period
AVTCL – VLAN Type Code Register Low
Frame Buffer Limit (max 4 KB). Multiple of 64 bytes (Default 0x40)
Reserved
VLANType_LOW: Lower 8 bits of the VLAN type code (Default 0x00)
Frame loopback.
0: Disable frame from sending back to its source port. (Default)
1: Allow frame to send back to its source port
In a regular ethernet switch, a packet should never be receive and forwarded to
the same port. Setting the bit allows it to happen.
This is not the same as an ingress MAC loopback. The destination MAC address
has to be stored (learned) in the MCT and associated with the originating source
port. The frame loopback will only work for unicast packets.
Reserved
Soft reset.
0: Normal operation (Default)
1: Reset. Not self clearing.
Flow Control Grant Period. (Default 0x3)
Units are (FCC[2:0]+1)*4us
Reserved
Zarlink Semiconductor Inc.
ZL50411
79
Data Sheet

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