zl50411 Zarlink Semiconductor, zl50411 Datasheet - Page 116

• Manufacturer Part Number: zl50411
• Description: Managed 9-port Fast Ethernet Switch With Private Vlan
• Manufacturer: Zarlink Semiconductor

12.3.9.13
CPU Address: h089C-089F
Accessed by CPU (R/W)
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Bits [5:0] in QOSC28 through QOSC31 represents one set of WFQ parameters for MMAC port. The granularity of
the numbers is 1, and their sum must be 64. QOSC31 corresponds to queue 3, that is the highest priority, and
QOSC27 corresponds to queue 0.
Default scheduling method will be strict priority across all queues. Only when the bit [7] is set, the queue will be
scheduled as WFQ. The credit number also works as shaper credit if bit [6] is set. A queue with shaper enabled will
be scheduled by strict priority when the token is available. The shaper setting override the WFQ (bit [7]) setting.
12.3.9.14
CPU Address: h08A4-08A7
Accessed by CPU (R/W)
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QOSC36 through QOSC39 represents one set of token limit on the shaper of MMAC port. The granularity of the
numbers is 64 bytes. The shaper is implemented as leaky bucket and the limit here works as bucket size. Since the
hardware implementation can keep negative number, the limit can be as small as one and still can transmit
oversized frame, as long as one byte token is available.
12.3.10
NOTE: Device Manufacturing test registers.
12.3.10.1
CPU Address: h0E00
Accessed by CPU (R/W)
Test group selection for testout[7:0].
QOSC28 – CREDIT_C00
QOSC29 – CREDIT_C01
QOSC30 – CREDIT_C02
QOSC31 – CREDIT_C03
QOSC36 – TOKEN_LIMIT_C00
QOSC37 – TOKEN_LIMIT_C01
QOSC38 – TOKEN_LIMIT_C02
QOSC39 – TOKEN_LIMIT_C03
Bits [5:0]:
Bit [6]:
Bit [7]:
(Group E Address) System Diagnostic
QOSC28 - QOSC31 - Classes WFQ Credit For MMAC
QOSC36 - QOSC39 - Shaper Control Port MMAC
DTSRL – Test Output Selection
Class scheduling credit
Traffic Shaper Enable
0: Disable
1: Enable
Enable WFQ Scheduling
0: Strict Priority
1: WFQ
Zarlink Semiconductor Inc.
ZL50411
116
Data Sheet