zl50411 Zarlink Semiconductor, zl50411 Datasheet

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... Supports IP Multicast with IGMP snooping Multicast groups ZL50411 MII 9-Port 10/100M Ethernet Switch RMII / MII / GPSI Quad Quad 10/100 10/100 PHY PHY Figure 1 - System Block Diagram 1 Zarlink Semiconductor Inc. ZL50411 Data Sheet April 2006 208-Ball LBGA 208-Ball LBGA** -40°C to +85°C 10/100 PHY ...

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... Achieves high buffer utilization while ensuring fairness among traffic classes and ports • Buffer reservations per class and per source port • Failover Features • Rapid link failure detection using hardware-generated heartbeat packets • link failover in less than 50 ms • Supports concentration mode ZL50411 2 Zarlink Semiconductor Inc. Data Sheet ...

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... The ZL50411 provides the ability to monitor a link, detect a simple link failure, and provide notification of the failure to the CPU. The CPU can then failover that link to an alternate link. The ZL50411 supports groups of port trunking/load sharing. Each group can contain ports. Port trunking/load sharing can be used to group ports between interlinked switches to increase the effective network bandwidth ...

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... Added section 1.6, “Default Switch Configuration and Initialization Sequence“ on page 23 • Added Private VLAN Edge (protected ports), force VLAN tag out, and unknown IP Multicast filtering support • Updated CPU timing diagrams to clarify P_A timing (13.4, “AC Characteristics and Timing“ on page 130) ZL50411 4 Zarlink Semiconductor Inc. Data Sheet ...

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... Added Reverse MII/GPSI timing characteristics (13.4.10, “Reverse General Purpose Serial Interface (RvGPSI)“ on page 139 and 13.4.11, “MII Management Data Interface (MDIO/MDC)“ on page 140) • Clarified that counter “DelayExceededDiscards” is not applicable for the ZL50411 (11.0, “Hardware Statistics Counters“ on page 53) December 2005 • ...

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... Register Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 3.1.2 Rx/Tx of Standard Ethernet Frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 3.1.3 Control Frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 3.2 I2C Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 3.2.1 Start Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 3.2.2 Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 3.2.3 Data Direction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 3.2.4 Acknowledgment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 3.2.5 Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 3.2.6 Stop Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 3.3 Synchronous Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 3.3.1 Write Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 3.3.2 Read Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 4.0 Data Forwarding Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 4.1 Unicast Data Frame Forwarding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 ZL50411 Table of Contents 6 Zarlink Semiconductor Inc. Data Sheet ...

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... Unicast Flow Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 7.7.2 Multicast Flow Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 7.8 Mapping to IETF Diffserv Classes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 7.9 Failover Backplane Feature 8.0 Port Trunking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 8.1 Features and Restrictions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 8.2 Unicast Packet Forwarding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 8.3 Multicast Packet Forwarding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 9.0 Traffic Mirroring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 9.1 Mirroring Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 9.2 Using port mirroring for loop back . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 ZL50411 Table of Contents 7 Zarlink Semiconductor Inc. Data Sheet ...

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... RMON – Ethernet Statistic Group (RFC 1757 11.4.1 Event Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 11.4.1.1 DropEvents 11.4.1.2 Octets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 11.4.1.3 Pkts 11.4.1.4 BroadcastPkts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 11.4.1.5 MulticastPkts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 11.4.1.6 CRCAlignErrors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 11.4.1.7 UndersizePkts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 11.4.1.8 OversizePkts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 11.4.1.9 Fragments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 11.4.1.10 Jabbers 11.4.1.11 Collisions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 11.4.1.12 Packet Count for Different Size Groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 11.5 Miscellaneous Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 12.0 Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 12.1 ZL50411 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 12.2 Directly Accessed Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 ZL50411 Table of Contents 8 Zarlink Semiconductor Inc. Data Sheet ...

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... CPURLSINFO0 - CPURLSINFO4 – Receive Queue Status . . . . . . . . . . . . . . . . . . . . . . . 92 12.3.4.21 CPUGRNCTR – CPU Granule Control 12.3.5 (Group 4 Address) Search Engine Group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 12.3.5.1 AGETIME_LOW – MAC address aging time Low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 12.3.5.2 AGETIME_HIGH –MAC address aging time High . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 12.3.5.3 SE_OPMODE – Search Engine Operation Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 ZL50411 Table of Contents 9 Zarlink Semiconductor Inc. Data Sheet ...

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... MIIC0 – MII Command Register 108 12.3.7.5 MIIC1 – MII Command Register 108 12.3.7.6 MIIC2 – MII Command Register 109 12.3.7.7 MIIC3 – MII Command Register 109 12.3.7.8 MIID0 – MII Data Register 109 12.3.7.9 MIID1 – MII Data Register 109 ZL50411 Table of Contents 10 Zarlink Semiconductor Inc. Data Sheet ...

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... PRTQOSST9A, PRTQOSST9B (MMAC port 119 12.3.10.10 CLASSQOSST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 12.3.10.11 PRTINTCTR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 12.3.10.12 QMCTRL0 120 12.3.10.13 QCTRL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 12.3.10.14 BMBISTR0, BMBISTR1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 12.3.10.15 BMControl 121 12.3.10.16 BUFF_RST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 12.3.10.17 FCB_HEAD_PTR0, FCB_HEAD_PTR1 122 12.3.10.18 FCB_TAIL_PTR0, FCB_TAIL_PTR1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 12.3.10.19 FCB_NUM0, FCB_NUM1 123 12.3.10.20 BM_RLSFF_CTRL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 12.3.10.21 BM_RSLFF_INFO[5: 124 ZL50411 Table of Contents 11 Zarlink Semiconductor Inc. Data Sheet ...

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... Media Independent Interface (MII 136 13.4.8 Reverse Media Independent Interface (RvMII 137 13.4.9 General Purpose Serial Interface (GPSI 138 13.4.10 Reverse General Purpose Serial Interface (RvGPSI 139 13.4.11 MII Management Data Interface (MDIO/MDC 140 13.4.12 JTAG (IEEE 1149.1-2001 141 ZL50411 Table of Contents 12 Zarlink Semiconductor Inc. Data Sheet ...

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... EN T M2_RX M2_C M2_TX M3_RX M3_C 1.2 Power and Ground Distribution G7-10, H7-10, J7-10, K7-10 GND D5, D12, E4, E13, M4, M13, 3.3V N5 D9, H4, H13, N7 1.8V ZL50411 P_DAT P_DAT P_DAT P_DAT P_DAT P_DAT A11 A13 P_DAT P_DAT P_DAT P_DAT P_DAT P_DAT A2 ...

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... N14, P14, R14, T14, N11, P11, R11, T11, N8, P8, R8, T8, N4, P4, R4, T4, N1, P1, R1, T1, J4, K3, K2, K1, F4, F3, G2, G1 ZL50411 Active low signal Input signal Input signal with Schmitt-Trigger Output signal (Tri-State driver) Input & Output signal with Tri-State driver Weak internal pull-up (nominal 100K Ω ) (refer to Section 1 ...

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... M9_COL B16 M9_RXCLK F14, F13, G14, G13 M9_RXD[3:0] A16 M9_TXEN A15 M9_MTXCLK ZL50411 I/O Ports [7:0] – Carrier Sense and Receive Data with pull-up Valid Output, slew Ports [7:0] – Transmit Enable This pin also serves as a bootstrap pin. Output, slew Ports [7:0] – Transmit Data Bit [3:0] Input Ports[7:0] – ...

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... G7-10, H7-10, J7-10 K7-10 Misc. D1 RESIN# C1 RESETOUT# F1 M_MDC F2 M_MDIO R7 M_CLK ZL50411 I/O Output [15:4] Reserved [3] EEPROM checksum is good [2] Initialization Completed [1] Memory Self Test in progress [0] Initialization started These pins also serve as bootstrap pins. Input JTAG - Test Data In with pull-up Input JTAG - Test Reset with pull-up In normal operation, this pin should be pulled low. Recommend weak external pull-down resistor (470 Ω ...

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... Bootstrap Pins External pull-up/down resistors are required on all bootstrap pins for proper operation. See “Bootstrap Options” on page 22 for more information. D2 TSTOUT[0] C3, D3, C2 TSTOUT[3:1] C5, C4, D4 TSTOUT[6:4] ZL50411 I/O Input MMAC Reference Clock with pull-up N/A Reserved. Leave unconnected. IC_GND Internal Connect. Tie to ground (V resistor ...

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... TSTOUT[10] C8 TSTOUT[11] C9 TSTOUT[12] C11, C10, D10 TSTOUT[15:13] K15, R15, R12, R9, M[7:0]_TXEN R5, R2, L2 Note: 1=pull-up; 0=pull-down ZL50411 I/O Input (Reset Only) EEPROM not installed. Pullup: Not installed Pulldown: Installed Input (Reset Only) Manufacturing Option. Must be pulled up. Must be externally pulled-up Input (Reset Only) Module Detect Pullup: Enable ...

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... Signal Mapping and Internal pull-up/Down Configuration The ZL50411 Fast Ethernet access ports (0-7) support 3 interface options: RMII, MII & GPSI. The table below summarizes the interface signals required for each interface and how they relate back to the Pin Symbol name shown in the “Ball Signal Description Table” on page 14. It also specifies whether the internal pull-up/down resistor is present for each pin in the specific operating mode ...

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... The ZL50411 Fast Ethernet uplink port (port 9) supports 1 interface option: MII. The table below summarizes the interface signals required for each interface, and how they relate back to the Pin Symbol name shown in “Ball Signal Description Table” on page 14. Fast Ethernet Uplink Port ...

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... The ZL50411 CPU access support 5 interface options 16-bit parallel, serial+MII (port 8), serial only, and unmanaged serial (with optional EEPROM). The table below summarizes the interface signals required for each interface, and how they relate back to the Pin Symbol name shown in “Ball Signal Description Table” on page 14. ...

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... Also, in unmanaged mode, an optional I the device at power-up or reset. TSTOUT[7] selects the EEPROM option. Ethernet Interface The ZL50411 supports module hotswap on all it's ports. This is enabled via TSTOUT[9]. When enabled, bootstrap pins M[7:0]_TXEN (ports 0-7) are used to specify the module type to support multiple ethernet interfaces during module hotswap ...

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... Default Switch Configuration and Initialization Sequence The ZL50411 will come out of reset in a default configuration, which will allow for basic L2 switching and automatic MAC address learning. In unmanaged mode, the default configuration will take effect immediately after reset. The default settings can be changed using the optional EEPROM. • ...

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... No VLAN ID hashing • Per-port Defaults • FE Ports - Link heart beat disabled • CPU Port - 100 M, Full Duplex, Flow Control - 8-byte header padding - per-source port buffer pool of 96 buffers, with flow control threshold of 48 buffers ZL50411 24 Zarlink Semiconductor Inc. Data Sheet ...

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... Power Sequencing The ZL50411 has two separate power supplies: V sequence is for applied first, followed by the V CC but by no more than 2 V. Both supplies may be powered-down simultaneously. >0 RESIN SCLK See “Typical Reset & Bootstrap Timing Diagram” on page 130 for more details on reset and bootstrap sampling. ...

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... Frame Engine (FE) and the external physical device (PHY). The MMAC implements an MII interface. The MMAC of the ZL50411 device meets the IEEE 802.3 specification able to operate in 10 M/100 M either Half or Full Duplex mode with a back pressure/flow control mechanism. Furthermore, it will automatically retransmit upon collision for total transmissions ...

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... Heartbeat Packet Generation and Response The ZL50411 provides the ability to monitor a link and detect a simple link failure. The Link Heart Beat (LHB) packet generation module allows simultaneous tracking of all the RMAC ports. Periodically, a LHB message will be sent for each link when inactivity is detected with in a programmable time period reply is not received in a specified amount of time, the failover detection module will identify a point-to-point failure for that link ...

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... BSR. However, the device is left in its normal functional mode. During this instruction, the BSR can be accessed by a data scan operation to take a sample of the functional data entering and leaving the device. The instruction is also used to preload test data into the BSR prior to loading an EXTEST instruction. ZL50411 28 Zarlink Semiconductor Inc. ...

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... Other available instructions for the ZL50411 include: • IDCODE – the IDCODE instruction causes the TDI and TDO to be connected to the IDCODE register. • HIGHZ – the HIGHZ instruction causes all of the logic outputs to be placed in an inactive drive state (e.g., high impedance) ...

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... Reg (Addr = 0) 8-bit only ) (Addr = 2) 16-bit Address 8-bit Data Bus Internal Registers Inderect Access Figure 4 - Overview of the 8/16-bit Interface ZL50411 Processor 3-bit Address 8/16-bit Data Bus Bus Address I/O Data MUX Command/ CPU Frame Reg Interrupt Reg Status Reg (Addr = 3) (Addr = 5) ...

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... Address CPU f rame Internal Transmit CPU f rame Registers FIFO Receiv e Inderect FIFO Access Figure 5 - Overview of the SSI Interface Zarlink Semiconductor Inc. ZL50411 Serial In Strobe Interrupt 16-bit Data Bus INT I/O Data MUX Command/ Control Command Interrupt Reg Status Reg 1 Reg (Addr = 5) ...

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... Register Configuration The ZL50411 has many programmable parameters, covering such functions as QoS weights, VLAN control, and port mirroring setup. In managed mode, the CPU interface provides an easy way of configuring these parameters. The parameters are contained in 8-bit configuration registers. The device allows indirect access to these registers, as follows: • ...

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... ZL50411 and de-assert RXDV after transmitting the last data To receive a frame into the CPU with MII interface: • ZL50411 acts as a PHY to provide transmit clock (TXCLK) to CPU so the CPU will depend on the transmit clock to receive packets from ZL50411 • ZL50411 has the ability to halt the transmit clock if the transmit FIFO of ZL50411 is under-run. CPU will ...

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... I C Interface The I²C interface serves the function of configuring the ZL50411 at boot time. The master is the ZL50411, and the slave is the EEPROM memory. The I²C interface uses two bus lines, a serial data line (SDA) and a serial clock line (SCL). The SCL line carries the control signals that facilitate the transfer of information from EEPROM to the switch ...

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... Start Condition Generated by the master (in our case, the ZL50411). The bus is considered to be busy after the Start condition is generated. The Start condition occurs if while the SCL line is High, there is a High-to-Low transition of the SDA line. Other than in the Start condition (and Stop condition), the data on the SDA line must be stable during the High period of SCL. The High or Low state of SDA can only change when SCL is Low. In addition, when the I² ...

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... ID bits are used to allow up to eight ZL50411 devices to share the same synchronous serial interface. The ID of each device can be setup by bootstrap. To reduce the number of signals required, the register address, command and data are shifted in serially through the DATAIN pin. STROBE- pin is used as the shift clock. DATAOUT pin is used as data return path. ...

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... There are 2 multicast queues for each of the 8 RMAC ports. There are 4 multicast queues for the MMAC and CPU ports. The mapping from the classified result to the priority queue is the same as the unicast traffic. By default, for the RMAC ports to map the 8 transmit priorities into 2 multicast queues, the 2 LSB are discarded. For the MMAC ZL50411 37 Zarlink Semiconductor Inc. ...

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... Basic Flow Shortly after a frame enters the ZL50411 and is written to the Frame Data Buffer (FDB), the frame engine generates a Switch Request, which is sent to the search engine. The switch request consists of the first 64 bytes of the frame, which contain all the necessary information for the search engine to perform its task. When the search engine is done, it writes to the Switch Response Queue, and the frame engine uses the information provided in that queue for scheduling and forwarding ...

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... The entry type is stored in the “status” field of the MCT data structure. 5.4 MAC Address Filtering The ZL50411's implementation of intelligent traffic switching provides filters for source and destination MAC addresses. This feature filters unnecessary traffic, thereby providing intelligent control over traffic flows and broadcast traffic. ...

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... Broadcast, unknown unicast or unknown multicast MAC address and unknown IP multicast address can also be filter on per VLAN basis. MAC address filtering allows the ZL50411 to block an incoming packet to an interface when it sees a specified MAC address in either the source address or destination address of the incoming packet. For example, if your network is congested because of high utilization from a MAC address, you can filter all traffic transmitted from that address and restore network flow, while you troubleshoot the problem ...

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... Definition” on page 62). For example, ports 1-3 might be assigned to the Marketing VLAN, ports 4-6 to the Engineering VLAN, and ports 7-9 to the Administrative VLAN. The ZL50411 determines the VLAN membership of each packet by noting the port on which it arrives. From there, the ZL50411 determines which outgoing port(s) is/are eligible to transmit each packet, or whether the packet should be discarded. ...

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... In addition, coordinating VLAN IDs across multiple switches enables VLANs to extend to multiple switches VLANs are supported in the ZL50411. When tag-based VLAN is enabled, each MAC address is learned with it associated VLAN. ...

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... IEEE 802.1Q Tag TPID = 0x8100 * Provider Tag TPID = Configurable on per device basis The value of the TPID of the Provider VLAN tag is not assigned in the IEEE 802.1ad standard. The ZL50411 provides a global configurable TPID but only supports the Extreme EtherType TPID (i.e. the stacked VLAN tag cannot equal 0x81-00) ...

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... The TxDMA will pull frame data from the memory and forward it granule-by-granule to the MAC TxFIFO of the destination port. 6.2 Frame Engine Details This section briefly describes the functions of each of the modules of the ZL50411 frame engine. 6.2.1 FCB Manager The FCB manager allocates FCB handles to incoming frames, and releases FCB handles upon frame departure. ...

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... It is also possible to add a class that has strict priority over all others; if this class has even one frame to transmit, then it goes first. In the ZL50411, each RMAC port will support two total classes, and the MMAC port will support four classes. We will discuss the various modes of scheduling these classes in the next section. ...

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... This provides per-class bandwidth partitioning with granular within 2%. In WFQ mode, though we do not assure frame latency, the ZL50411 still retains a set of dropping rules that helps to prevent congestion and trigger higher level protocol end-to-end flow control. ...

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... Such a temporary region is necessary, because when the frame first enters the ZL50411, its destination port and class are as yet unknown, and so the decision to drop or not needs to be temporarily postponed. This ensures that every frame can be received first before subjecting them to the frame drop discipline after classifying ...

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... RED (at B%). If total multicast resources reaches MCC, the frame will be dropped. All the 100% dropping functions are disabled if the source port is flow control capable, however, RED (at B%) will still be applied. ZL50411 Temporary reservation R R ...

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... Xon is triggered when a port is currently being flow controlled, and all of that port’s reserved FDB slots have been released. Note that the ZL50411’s per-source-port FDB reservations assure that a source port that sends a single frame to a congested destination will not be flow controlled. ...

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... On the receiving side, the MAC will also monitor the activity. If there is no good packet received for more than 2X the set period, an alarm will be raised to the CPU. The LHB packet is only used by the ZL50411 to reset the timeout counter ignored otherwise (i.e. not passed on within the system). ...

Page 51

... If a VLAN includes any of the ports in a trunk group, all the ports in that trunk group should be in the same VLAN member map. The ZL50411 also provides a safe fail-over mode for port trunking automatically. If one of the ports in the trunking group goes down, the ZL50411 can redistribute the traffic over to the remaining ports in the trunk with software assistance ...

Page 52

... DEVICE A 10.0 Clocks 10.1 Clock Requirements 10.1.1 System Clock (SCLK) Speed Requirement SCLK is the primary clock for the ZL50411 device. The speed requirement is based on the system configuration. Below is a table for a few configuration. Configuration 6-9 ports 10/100 M 1-5 ports 10/100 M ZL50411 Figure 13 - Remote Loopback Test Table 11 - SCLK Speed Requirements 52 Zarlink Semiconductor Inc ...

Page 53

... Hardware Statistics Counters List ZL50411 hardware provides a full set of statistics counters for each Ethernet port. The CPU accesses these counters through the CPU interface. All hardware counters are rollover counters. When a counter rolls over, the CPU is interrupted, so that long-term statistics may be kept. The MAC detects all statistics, except for the filtering ...

Page 54

... Counts the number of frames of valid frame length that have been received on this port. Frame size: No FCS (i.e. checksum) error No collisions Use ZL50411 counter “Total Frames Received”, C[8]. Note: max. frame size may be BUF_LIMIT, if enabled on this port. 11.2.1.2 PortReadableOctets Counts the number of bytes (i.e. octets) contained in valid frames that have been received on this port. ...

Page 55

... Frame size: Framing error FCS error No collisions Use ZL50411 counter “Alignment Error”, C[21]. Note: when this counter is incremented, the ZL50411 also increments the “CRC” counter, C[23]. 11.2.1.5 PortFrameTooLongs Counts number of frames received with size exceeding the maximum allowable frame size. Frame size: Framing error: don’ ...

Page 56

... Frame size: Use ZL50411 counter “Collision”, C[25]. 11.2.1.9 PortLateEvents Counts number of collision events that occurred late (after LateEventThreshold = 64 bytes). Frame size: Use ZL50411 counter “Port Late Collision”, C[29]. ZL50411 Min. Frame Size Max. Frame Size < 10 bytes Min. Frame Size Max. Frame Size > ...

Page 57

... Counts number of frames received with size larger than Jabber Lockup Protection Timer (TW3 = 000 bit times – 20% + 50%). Frame size: No ZL50411 counter. Note: the ZL50411 defines a jabber frame as any frame that exceeds 6400 bytes, however, the maximum buffer size supported by the device is 4 KBytes. Thus, any frame > 4KB would be counted as an Oversized Frame, C[15]. 11.2.1.11 PortDataRateMisatches For repeaters or HUB application only ...

Page 58

... Counts the total number of octets (i.e. bytes) in any frames received. Frame size: No framing error FCS error: don’t care No collisions Use ZL50411 counter “Bytes Received”, C[5]. Note: max. frame size may be BUF_LIMIT, if enabled on this port. 11.4.1.3 Pkts Counts the number of frames received, good or bad. ...

Page 59

... Framing error and/or FCS error No collisions Use ZL50411 counters “CRC”, C[23], and “Alignment Error”, C[21]. Note: when the “Alignment Error” counter, C[21], is incremented, the ZL50411 also increments the “CRC” counter, C[23], thus, the CRC counter can be used for this statistic. 11.4.1.7 UndersizePkts Counts number of frames received with size less than 64 bytes ...

Page 60

... Framing error: don’t care FCS error No collisions No ZL50411 counter. Note: the ZL50411 defines a jabber frame as any frame that exceeds 6400 bytes, however, the maximum buffer size supported by the device is 4 KBytes. Thus, any frame > would be counted as an Oversized Frame, C[15]. ZL50411 Min. Frame Size Max ...

Page 61

... Note: the ZL50411 doesn’t include bad frames in the above counters. 11.5 Miscellaneous Counters In addition to the statistics groups defined in previous sections, the ZL50411 has other statistics counters for its own purposes. 1. Flow control – one counting the number of flow control frames received, C[9], and another counting the number of flow control frames sent, C[3]. 2. Frames sent – ...

Page 62

... Register Definition 12.1 ZL50411 Register Description Register 0. ETHERNET Port Control Registers (Substitute [n] with Port number (0..9)) ECR1Pn Port Control Register 1 for Port n ECR2Pn Port Control Register 2 for Port n ECR3Pn Port Control Register 3 for Port n ECR4Pn Port Control Register 4 for Port n BUF_LIMIT Frame Buffer Limit ...

Page 63

... CPURLSINFO[4:0] CPUGRNCTR 4. Search Engine Configurations AGETIME_LOW MAC Address Aging Time Low AGETIME_HIGH MAC Address Aging Time High SE_OPMODE Search Engine Operating Mode Table 12 - Register Description (continued) ZL50411 CPU Addr Description (Hex) 0228+2n 0229+2n 0300 0301 0302 0303 0304 0305 0306 0310+n ...

Page 64

... Priority WLPP76 Well Known Logic Port 6 and 7 Priority WLPE Well Known Logic Port Enable WLPFD Well Known Logic Port Force Discard Enable Table 12 - Register Description (continued) ZL50411 CPU Addr Description (Hex) 0500 0510 0511 0512 0513 0514 0515 ...

Page 65

... MII Command Register 2 MIIC3 MII Command Register 3 MIID0 MII Data Register 0 MIID1 MII Data Register 1 USD One micro second divider DEVICE Device id and test Table 12 - Register Description (continued) ZL50411 CPU Addr Description (Hex) 0570+2n 0571+2n 0590 0591 0592 0593 0594 0595 ...

Page 66

... Address 0 MIRROR_SRC_MAC1 Mirror Source MAC Address 1 MIRROR_SRC_MAC2 Mirror Source MAC Address 2 MIRROR_SRC_MAC3 Mirror Source MAC Address 3 MIRROR_SRC_MAC4 Mirror Source MAC Address 4 Table 12 - Register Description (continued) ZL50411 CPU Addr Description (Hex) 060B 0610 0611 0612 0613 0614 0620 0621 0622 0700 0701 ...

Page 67

... TESTOUT0 Testmux Output [7:0] TESTOUT1 Testmux Output [15:8] MASK0 MASK Timeout 0 MASK1 MASK Timeout 1 MASK2 MASK Timeout 2 MASK3 MASK Timeout 3 MASK4 MASK Timeout 4 Table 12 - Register Description (continued) ZL50411 CPU Addr Description (Hex) 070B 070C 0710 0711 0800+n 0820+n 0840+n 0848 0849 0860+n 0868 ...

Page 68

... Number [14:8] BM_RLSFF_CTRL Read control register BM_RLSFF_INFO0 Bm_rlsfifo_info[7:0] BM_RLSFF_INFO1 Bm_rlsfifo_info[15:8] BM_RLSFF_INFO2 Bm_rlsfifo_info[23:16] BM_RLSFF_INFO3 Bm_rlsfifo_info[31:24] BM_RLSFF_INFO4 Bm_rlsfifo_info[39:32] BM_RLSFF_INFO5 Fifo_cnt[2:0],Bm_rlsfifo_inf o[44:40] Table 12 - Register Description (continued) ZL50411 CPU Addr Description (Hex) 0E80-0E82 0E90+n 0EA0+n 0EA8 0EA9 0EAA 0EAB 0EAC 0EAD 0EB0+n 0EBA 0EBB 0EBC 0EBD ...

Page 69

... CPU Interface [15:0] INDEX 8-bit CPU Interface [7:0] INDEX_L INDEX_REG1 Used to write the address of the indirect register to be accessed. 8-bit CPU Interface Only Bit # Name [7:0] INDEX_H ZL50411 CPU Addr Description (Hex) 0F00 0F01 0F02 0F03 0F04 0FFF Type Description W 16-bit address of the indirect register ...

Page 70

... CPU_FRAME W R 8-bit CPU Interface [7:0] CPU_FRAME W R Register Table CPU_FRAME_REG ZL50411 Default: 00 Description 8-bit indirect register data Register Table DATA_REG Default: 00 Description Send Ethernet frame to CPU MAC. Bits [7:0] is even byte, [15:8] is odd byte. Data sequence specified in Processor Interface application note, ZLAN-26 ...

Page 71

... RXFIFO_REALIGN W TXFIFO_EOF R [7:6] RSVD R/W Register Table CMD_STATUS_REG ZL50411 Width 8-bit Default: 00 Description Set Control Frame Receive buffer ready, after CPU writes a complete frame into the buffer. This bit is self-cleared. Control Frame receive buffer ready, CPU can write a new frame 1 – CPU can write a new control command 0 – ...

Page 72

... Type 16-bit or serial CPU Interface [15:0] CTL_BUF1 W R Register Table CTL_FRAME_BUF1 ZL50411 Default: N/A Description Ethernet frame interrupt. Ethernet Frame receive buffer has data for processor to read Control frame 1 interrupt. Control Frame receive buffer 1 has data for processor to read Control frame 2 interrupt. Control Frame receive buffer 2 has data ...

Page 73

... Flow Control 0 - Enable (Default Disable Bit [1] Duplex Mode 0 - Full Duplex (Default Half Duplex - Only in 10/100 mode ZL50411 W Send control frame to command engine Control frame format specified in Processor Interface application note, ZLAN-26. R Receive control frame from command engine Control frame format specified in Processor Interface application note, ZLAN-26 ...

Page 74

... Bit [1] Duplex Mode Must Full Duplex (Default) Bit [2] Speed 0 - 100 Mbps (Default Mbps ZL50411 Frame is dropped Frame is dropped Frame is dropped. Source MAC address is learned. Frame is forwarded. Source MAC address is learned. (Default) Frame is dropped Frame is dropped Frame is dropped. Source MAC address is learned. ...

Page 75

... If this feature is enabled, a packet leaving the device will ALWAYS have a VLAN tag. Only applicable in tagged-based VLAN mode (PVMODE[0]=’1’). In port-based VLAN mode (PVMODE[0]=’0’), this bit must be 0. ZL50411 Frame is dropped Frame is dropped Frame is dropped. Source MAC address is learned. ...

Page 76

... Disable (Default) 1: Enable Bits [7:6] Security Enable. The ZL50411 checks the incoming data for one of the following conditions: • If the source MAC address of the incoming packet is in the MAC table and is defined as secure address but the ingress port is not the same as the port associated with the MAC address in the MAC table. • ...

Page 77

... MCT and associated with the originating source port. The frame loopback will only work for unicast packets. Bit [6]: Link Heart Beat Receive 0: Disable (Default). Also clears all MAC LHB status. 1: Enable Bit [7]: Soft reset. 0: Normal operation (Default) 1: Reset. Not self clearing. ZL50411 77 Zarlink Semiconductor Inc. Data Sheet ...

Page 78

... In this mode, the packet is looped back in the MAC layer before going out of the chip. You must force linkup at full duplex as well. External loopback is another level of system diagnostic which involves the PHY device to loopback the packet. Bits [4:3]: Interface mode MII mode (Default) ZL50411 78 Zarlink Semiconductor Inc. Data Sheet ...

Page 79

... Units are (FCC[2:0]+1)*4us Bits [7:3]: Reserved 12.3.2 (Group 1 Address) VLAN Group 12.3.2.1 AVTCL – VLAN Type Code Register Low I²C Address: h028; CPU Address: h0100 Accessed by CPU and I²C (R/W) Bits [7:0]: VLANType_LOW: Lower 8 bits of the VLAN type code (Default 0x00) ZL50411 79 Zarlink Semiconductor Inc. Data Sheet ...

Page 80

... In Tag based VLAN Mode Bits [3:0]: PVID [11:8] (Default is 0xF) Bit [4]: Untrusted Port. This register is used to change the VLAN priority field of a packet to a predetermined priority. 1: VLAN priority field is changed to Bit [7:5] at ingress port (Default) 0: Keep VLAN priority field ZL50411 80 Zarlink Semiconductor Inc. Data Sheet ...

Page 81

... Force untag out (VLAN tagging is based on IEEE 802.1Q rule Disable (Default Force untagged output. All packets transmitted from this port are untagged. This bit is used when this port is connected to legacy equipment that does not support VLAN tagging. ZL50411 81 Zarlink Semiconductor Inc. Data Sheet ...

Page 82

... Same function as SE_OPMODE bit [7]. Either bit can enable the function; both need to be turned off to disable the feature. Bit [2]: Disable dropping of frames with destination MAC addresses 01-80-C2-00-00-01 to 0x01-80-C2-00-00-0F. 0: Drop all frames in this range (Default) 1: Disable dropping of frames in this range ZL50411 82 Zarlink Semiconductor Inc. Data Sheet ...

Page 83

... Bits [7:0] represent ports 9,7-0, excluding the source port. For example: For port 0, [7:0] represent ports 9,7..1 For port 1, [7:0] represent ports 9,7..2,0 For port 2, [7:0] represent ports 9,7..3,1..0 12.3.3 (Group 2 Address) Port Trunking Groups Trunk Group – eight RMAC ports can be selected for each trunk group. ZL50411 83 Zarlink Semiconductor Inc. Data Sheet ...

Page 84

... Hash result 3 destination port number (Default 0) 12.3.3.4 TRUNKn_HASH54 – Trunk group n hash result 5/4 destination port number CPU Address: h020A+ trunk group) Accessed by CPU (R/W) Bits [3:0] Hash result 4 destination port number (Default 0) Bits [7:4] Hash result 5 destination port number (Default 0) ZL50411 TRUNK0 ...

Page 85

... Bits [7:0]: Port 7-0 bit map for multicast hash. (Default 0xFF) 12.3.3.7 MULTICAST_HASHn-1 – Multicast hash result 0~7 mask byte 1 CPU Address: h0229+ hash value) Accessed by CPU (R/W) Bits [1:0]: Port 9-8 bit map for multicast hash. (Default 0x3) ZL50411 HASH0-1 HASH0-0 HASH1-1 HASH1-0 HASH2-1 HASH2-0 HASH3-1 HASH3-0 ...

Page 86

... Accessed by CPU (R/W) Bits [7:0]: Byte 0 (bits [7:0]) of the CPU MAC address (Default 0) 12.3.4.2 MAC1 – CPU MAC address byte 1 CPU Address: h0301 Accessed by CPU (R/W) Bits [7:0]: Byte 1 (bits [15:8]) of the CPU MAC address (Default 0) ZL50411 MAC3 MAC2 MAC1 MAC0 86 Zarlink Semiconductor Inc. Data Sheet 0 (MC bit) ...

Page 87

... CPU frame interrupt. CPU frame buffer has data for CPU to read Bit [1]: Control Command 1 interrupt. Control Command Frame buffer1 has data for CPU to read Bit [2]: Control Command 2 interrupt. Control command Frame buffer2 has data for CPU to read Bits [6:3]: Reserved Bit [7]: Device Timeout Detected interrupt ZL50411 87 Zarlink Semiconductor Inc. Data Sheet ...

Page 88

... Accessed by CPU (RW) Select which receive queue is being used by the CPU port. Bit [0]: Select Queue 0 0: Not selected (Default) 1: Selected Bit [1]: Select Queue 1 Bit [2]: Select Queue 2 Bit [3]: Select Queue 3 Bit [4]: Select Multicast Queue 0 Bit [5]: Select Multicast Queue 1 ZL50411 88 Zarlink Semiconductor Inc. Data Sheet ...

Page 89

... MAC01, MAC23, MAC45, MAC67, and MAC9 registers are used with the MAC0~5 registers to form the CPU MAC address on a per port basis. 12.3.4.13 MAC23 – Increment MAC port 2,3 address CPU Address: h0326 Accessed by CPU (RW) Bits [2:0]: Bits [42:40] of Port 2 CPU MAC address Bit [3]: Reserved Bits [6:4]: Bits [42:40] of Port 3 CPU MAC address Bit [7]: Reserved ZL50411 89 Zarlink Semiconductor Inc. Data Sheet ...

Page 90

... CPUQINS0 - CPUQINS6 – CPU Queue Insertion Command CPU Address: h0330-0336 Accessed by CPU, (R/W) 55 CQ6 CQ5 CPU Queue insertion command CPUQINS0 Bit[7:0]: Destination Map (port 7-0). CPUQINS1 Bit[9:8]: Destination Map (MMAC, CPU). Bits [13:10] Priority ZL50411 CQ4 CQ3 CQ2 CQ1 90 Zarlink Semiconductor Inc. Data Sheet 0 CQ0 ...

Page 91

... Bit [0]: Insertion Fail (May be due to queue full, WRED or filtering) Bit [1]: 12.3.4.19 CPUGRNHDL0 - CPUGRNHDL1 – CPU Allocated Granule Pointer CPU Address: h0338-339 Accessed by CPU, (RO) CPU Queue insertion command Granule pointer. Bits [14:0]: Pointer valid Bit [15]: ZL50411 15 0 CG1 CG0 91 Zarlink Semiconductor Inc. Data Sheet ...

Page 92

... AGETIME_LOW – MAC address aging time Low I²C Address: h049; CPU Address: h0400 Accessed by CPU and I²C (R/W) Used in conjuction with AGETIME_HIGH. The ZL50411 removes the MAC address from the data base and sends a Delete MAC Address Control Command to the CPU. Bits [7:0]: Low byte of the MAC address aging timer (Default 0x5C) 12 ...

Page 93

... Enable slow learning. Learning is temporary disabled when search demand is high 12.3.6 (Group 5 Address) Buffer Control/QOS Group 12.3.6.1 QOSC – QOS Control I²C Address: h04B; CPU Address: h0500 2 Accessed by CPU and I C (R/W) Bit [0]: Enable TX rate control (on RMAC ports only) 0 – Disable (Default) 1 – Enable ZL50411 93 Zarlink Semiconductor Inc. Data Sheet ...

Page 94

... Global congestion control on the multicast granule count. Used to trigger 100% drop (or flow control enabled on source port) when total multicast granule count reaches MCC. Granularity is 16 granule (Default 0x6). See Programming QoS Registers application note, ZLAN-42, for more information ZL50411 94 Zarlink Semiconductor Inc. Data Sheet ...

Page 95

... CPU Address: h0515 Accessed by CPU (R/W) Bits [3:0]: Corresponds to the frame drop percentage RB% for ingress rate control. Granularity 6.25%. Bits [7:4]: Corresponds to the frame drop percentage RA% for ingress rate control. Granularity 6.25%. See Rate Control application note, ZLAN-33, for more information ZL50411 95 Zarlink Semiconductor Inc. Data Sheet ...

Page 96

... VLAN priority field. For example, programming a value of 7 into bit 2:0 of the AVPML register would map packet VLAN priority 0 into Internal transmit priority 7. The new priority is used inside the ZL50411. When the packet goes out it carries the original priority. ZL50411 96 Zarlink Semiconductor Inc ...

Page 97

... Map VLAN priority into frame discard when low priority buffer usage is above threshold Bit [0]: Frame drop precedence when VLAN Tag priority field is 0 (Default 0) 0 – Drop Precedence Level 0 (Lowest) (Default) 1 – Drop Precedence Level 1 (Highest) ZL50411 97 Zarlink Semiconductor Inc. Data Sheet ...

Page 98

... Map TOS field in IP packet into eight level transmit priorities Bit [0]: Priority when the TOS field is 2 (Default 0) Bits [3:1]: Priority when the TOS field is 3 (Default 0) Bits [6:4]: Priority when the TOS field is 4 (Default 0) Bit [7]: Priority when the TOS field is 5 (Default 0) ZL50411 98 Zarlink Semiconductor Inc. Data Sheet ...

Page 99

... USER_PROTOCOL_n – User Define Protocol 0~7 I²C Address: h0B3+n; CPU Address: h0550+n Accessed by CPU and I²C (R/W) (Default 00) This register is duplicated eight times from PROTOCOL 0~7 and allows the CPU to define eight separate protocols. Bits [7:0]: User Define Protocol ZL50411 99 Zarlink Semiconductor Inc. Data Sheet ...

Page 100

... Enable Protocol 7 Force Discard User Defined Logical Ports and Well Known Ports The ZL50411 supports classifying packet priority through layer 4 logical port information. It can be setup by 8 Well Known Ports, 8 User Defined Logical Ports, and 1 User Defined Range. The 8 Well Known Ports supported are: • ...

Page 101

... Accessed by CPU and I²C (R/W) Bits [3:0]: Priority setting, transmission + dropping, for Well known port 6 (22 for ssh) Bits [7:4]: Priority setting, transmission + dropping, for Well known port 7 (554 for rtsp) ZL50411 0 – Drop Precedence Level 0 (Lowest) (Default) 1 – Drop Precedence Level 1 (Highest) Transmit Priority Level 1 ... ...

Page 102

... Enable Well Known Port 3 Force Discard Bit [4]: Enable Well Known Port 4 Force Discard Bit [5]: Enable Well Known Port 5 Force Discard Bit [6]: Enable Well Known Port 6 Force Discard Bit [7]: Enable Well Known Port 7 Force Discard ZL50411 102 Zarlink Semiconductor Inc. Data Sheet ...

Page 103

... Accessed by CPU and I²C (R/W) Bits [3:0]: Priority setting, transmission + dropping, for logic port 2 Bits [7:4]: Priority setting, transmission + dropping, for logic port 3 (Default 00) ZL50411 TCP/UDP Logic Port Low TCP/UDP Logic Port High 0 – Drop Precedence Level 0 (Lowest) (Default) 1 – Drop Precedence Level 1 (Highest) Transmit Priority Level 1 ...

Page 104

... USER_PORT_FORCE_DISCARD[7:0] – User Define Logic Port 0~7 Force Discard I²C Address: h0A7; CPU Address: h0595 Accessed by CPU and I²C (R/W) Bit [0]: Enable User Port 0 Force Discard 1 – Enable 0 – Disable Bit [1]: Enable User Port 1 Force Discard ZL50411 104 Zarlink Semiconductor Inc. Data Sheet ...

Page 105

... Lower 8 bit of the User Define Logical Port High Range 12.3.6.38 RHIGHH – User Define Range High Bit 15:8 I²C Address: h0B1; CPU Address: h05A3 Accessed by CPU and I²C (R/W) Bits [7:0]: Upper 8 bit of the User Define Logical Port High Range ZL50411 105 Zarlink Semiconductor Inc. Data Sheet ...

Page 106

... Disable jabber detection. This is for HomePNA applications or any serial operation slower than 10 Mbps Enable 1 = Disable Bits [6] Reserved Bit [7]: Half duplex flow control feature 0 = Half duplex flow control always enable 1 = Half duplex flow control by negotiation ZL50411 106 Zarlink Semiconductor Inc. Data Sheet ...

Page 107

... HASH index for learning/searching. This is to allow Independent VLAN Learning (IVL). This feature is only applicable in tagged-based VLAN mode (PVMODE[0]=’1’). In port-based VLAN mode (PVMODE[0]=’0’), this bit must be ‘0’. ZL50411 107 Zarlink Semiconductor Inc. Data Sheet ...

Page 108

... Bits [7:0]: MII Command Data [7:0] Note : Before programming MII command: set FEN[6]; check MIIC3, making sure RDY; then program MII command. 12.3.7.5 MIIC1 – MII Command Register 1 CPU Address: h0604 Accessed by CPU (R/W) Bits [7:0]: MII Command Data [15:8] ZL50411 108 Zarlink Semiconductor Inc. Data Sheet ...

Page 109

... Note : Writing to this register will initiate a serial management cycle to the MII management interface. 12.3.7.8 MIID0 – MII Data Register 0 CPU Address: h0607 Accessed by CPU (RO) Bits [7:0]: MII Data [7:0] 12.3.7.9 MIID1 – MII Data Register 1 CPU Address: h0608 Accessed by CPU (RO) Bits [7:0]: MII Data [15:8] ZL50411 109 Zarlink Semiconductor Inc. Data Sheet ...

Page 110

... The checksum formula is: FF Σ I²C register = When the ZL50411 boots from the EEPROM the checksum is calculated and the value must be zero. If the checksum is not zeroed the ZL50411 does not start and pin CHECKSUM_OK is set to zero. ZL50411 110 Zarlink Semiconductor Inc. ...

Page 111

... I²C Address: h0C0; CPU Address: h0621 Accessed by CPU and I²C (R/W) Bits [7:0] FCB Base address bit 15:8 (Default 0x60) 12.3.7.18 FCB Base Address Register 2 I²C Address: h0C1; CPU Address: h0622 Accessed by CPU and I²C (R/W) Bits [7:0] FCB Base address bit 23:16 (Default 0) ZL50411 111 Zarlink Semiconductor Inc. Data Sheet ...

Page 112

... RMII_MIRROR0 – RMII Mirror 0 CPU Address: h0710 Accessed by CPU (R/W) Bits [2:0]: Source port to be mirrored Bit [3]: Mirror path 0: Receive 1: Transmit Bits [6:4]: Destination port for mirrored traffic Bit [7]: Mirror enable ZL50411 DEST_MAC3 DEST_MAC2 DEST_MAC1 [31:24] [23:16] [15:8] (Default 00) (Default 00) (Default 00) SRC_MAC3 SRC_MAC2 SRC_MAC1 [31:24] [23:16] [15:8] ...

Page 113

... Once the packet rate is reached, packets will be dropped. To turn off the rate limit, program the field to 0. Time base is based on register FCR0 [6:4] Bits [3:0]: Multicast Rate Control. Number of multicast packets allowed within the time defined in bits the Flooding Control Register (FCRn). (Default 0). ZL50411 113 Zarlink Semiconductor Inc. Data Sheet ...

Page 114

... PTHG – Port MMAC Threshold I²C Address: h0CA; CPU Address: h0869 Accessed by CPU and I²C (R/W) Expressed in multiples of 16 granules. More than this number used on a source port will trigger either random drop or flow control (Default 0x12) ZL50411 114 Zarlink Semiconductor Inc. Data Sheet ...

Page 115

... Multiple of 16 granules. The two numbers set the two level for WRED on the high priority queue. When the queue size exceeds the L1 threshold, received frame will subject to X% (high drop (low drop) WRED. When the queue size exceeds L2 threshold, received frame will either be filtered (high drop) or subject to Z% WRED. ZL50411 115 Zarlink Semiconductor Inc. ...

Page 116

... E Address) System Diagnostic NOTE: Device Manufacturing test registers. 12.3.10.1 DTSRL – Test Output Selection CPU Address: h0E00 Accessed by CPU (R/W) Test group selection for testout[7:0]. ZL50411 116 Zarlink Semiconductor Inc. Data Sheet ...

Page 117

... Bootstrap value from TSTOUT[15:0]: Bit [6:0]: TSTOUT[6:0] Bit [8:7]: Invert of TSTOUT[8:7] Bit [9]: TSTOUT[11] Bit [10]: TSTOUT[9] Bit [11]: TSTOUT[10] Bit [14:12]: TSTOUT[14:12] Bit [15]: Always 0 Bits [23:16]: Bootstrap value from M[7:0]_TXEN Bit [16]: M0_TXEN Bit [17]: M1_TXEN ... Bit [23]: M7_TXEN Bits [31:24]: Reserved ZL50411 23 15 BT2 BT1 117 Zarlink Semiconductor Inc. Data Sheet 0 BT0 ...

Page 118

... High priority queue reach L1 WRED level Bit [4]: High priority queue reach L2 WRED level Bit [5]: Low priority MC queue full Bit [6]: High priority MC queue full Bit [7]: 12.3.10.8 PRTQOSST8A, PRTQOSST8B (CPU port) CPU Address: h0EA8 – 0EA9 Accessed by CPU (RO) 15 ZL50411 PQSTB PQSTA 118 Zarlink Semiconductor Inc. Data Sheet 0 ...

Page 119

... Bit [7]: Priority queue 2 reach L2 WRED level Bit [8]: Priority queue 3 reach L1 WRED level Bit [9]: Priority queue 3 reach L2 WRED level Bit [10]: Priority 0 MC queue full Bit [11]: Priority 1 MC queue full Bit [12]: Priority 2 MC queue full ZL50411 0 PQSTA 119 Zarlink Semiconductor Inc. Data Sheet ...

Page 120

... CPU Address: h0EB0+n Accessed by CPU (R/W) Bit [0]: Suspend port scheduling (no departure) Bit [1]: Reset queue Bits [4:2]: Reserved Bit [5]: Force out MAC control frame Bit [6]: Force out XOFF flow control frame Bit [7]: Force out XON flow control frame ZL50411 120 Zarlink Semiconductor Inc. Data Sheet ...

Page 121

... BMBISTR0, BMBISTR1 CPU Address: h0EBB - 0EBC Accessed by CPU (RO) 12.3.10.15 BMControl CPU Address: h0EBD Accessed by CPU (R/W) Bits [3:0]: Block Memory redundancy control 0: Use hardware detected value All others: Overwrite the hardware detected memory swap map Bits [7:4]: Reserved ZL50411 121 Zarlink Semiconductor Inc. Data Sheet ...

Page 122

... Bits [7:0] CPU address: h0EC2 Accessed by CPU (R/W) Fcb_head_ptr[14:8]. The head pointer of free granule link that CPU assigns. Bits [6:0] Set 1 to write Bit [7] If CPU wants to write again, CPU has to clear bit 15 and then set bit 15. ZL50411 122 Zarlink Semiconductor Inc. Data Sheet ...

Page 123

... The information of BM release FIFO is relocated to registers BM_RLSFF_INFO (address ECD, ECC, ECB, ECA, EC9 and EC8). If the FIFO is not empty, CPU can read out the next by setting the bit 0. Read only happens when bit 0 is changing from ZL50411 123 Zarlink Semiconductor Inc. ...

Page 124

... Accessed by CPU (RO) Bits [4:0] Rls_count[6:2] Bit [ then It is multicast packet. Bits [7:6] Rls_src_port[1:0[ CPU address: h0ECD Accessed by CPU (RO) Bits [1:0] Rls_src_port[3:2] Bits [3:2] Class[1:0] Bit [4] This release request is from QM directly. Bits [7:5] Entries count in release FIFO, 0 means FIFO is empty ZL50411 124 Zarlink Semiconductor Inc. Data Sheet ...

Page 125

... This bit is reserved in unmanaged mode. In managed mode, the CPU writes this bit with ‘1’ to indicate initialization is completed and ready to forward packets. The ‘0' to '1' transition will toggle TSTOUT[2] from low to high. Bits [7:5]: Reserved ZL50411 125 Zarlink Semiconductor Inc. Data Sheet ...

Page 126

... Not busy (not reading configuration from I²C) Bit [2]: 1: BIST in progress 0: BIST not running Bit [3]: 1: RAM Error 0: RAM OK Bits [5:4]: Device Signature 10: ZL50411 device Bits [7:6]: Revision 00: Initial Silicon 01: Second Silicon 10: Third Silicon 12.3.11.3 DCR1 - Device Status Register 1 CPU Address: h0F02 Accessed by CPU (RO) ...

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... Note: If Module Detect feature is disabled (bootstrap TSTOUT[9]=’0’), this bit will always be ‘1’. 12.3.11.6 DA – Dead or Alive Register CPU Address: h0FFF Accessed by CPU (RO) Always return 8’ Indicate the CPU interface or serial port connection is good. Bits [7:0] Always return DA ZL50411 127 Zarlink Semiconductor Inc. Data Sheet ...

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... Caution: Stress above those listed may damage the device. Exposure to the Absolute Maximum Ratings for extended periods may affect device reliability. Functionality at or above these limits is not implied. 13.2 DC Electrical Characteristics V = 3.3 V +/- 10 1.8 V +/- 5% DD ZL50411 -65 ° +150 ° C -40 ° +85 ° C +125 ° C +2. +3. +1. + ...

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... OUT C I/O Capacitance I/O θ Thermal resistance with 0 air flow ja θ Thermal resistance with 1 m/s air flow ja θ Thermal resistance with 2 m/s air flow ja θ Thermal resistance between junction and case jc ZL50411 Min. 2.4 2.0 < < OUT CC 129 Zarlink Semiconductor Inc. Data Sheet Typ. Max. ...

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... R1 Bootstrap Pins Outputs Figure 14 - Typical Reset & Bootstrap Timing Diagram Symbol Parameter R1 Delay until RESETOUT# is tri-stated R2 Bootstrap stabilization R3 RESETOUT# assertion ZL50411 Tri-Stated R3 Inputs R2 Min. Typ RESETOUT# state is then determined by the external pull-up/down resistor 1 µ µ s Bootstrap pins sampled on rising edge of ...

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... T WS Write Active Time T WA Write Hold Time T WH Write Recovery time T WR Data Set Up time T DS Data Hold time T DH ZL50411 Activ e Tim e R ecov ery Tim ATA0 H old tim e ...

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... T RS Read Active Time T RA Read Hold Time T RH Read Recovery time T RR Data Valid time T DV Data Invalid time T DI ZL50411 Activ e Tim e R ecov ery Tim ATA0 Inv alid tim e ...

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... DATAOUT output delay time D3** D4 STROBE low time D5 STROBE high time STROBE frequency of operation * Open Drain Output. Low to High transition is controlled by external pullup resistor. ** Totem Pole Output. ZL50411 Figure 17 - SSI Setup & Hold Timing D3-max D3-min Figure 18 - SSI Output Delay Timing Parameter Min ...

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... EEPROM Inter-Integrated Circuit (I²C) Symbol S1 SDA input setup time S2 SDA input hold time S3* SDA output delay time * Open Drain Output. Low to High transition is controlled by external pullup resistor. ZL50411 SCL S1 SDA Figure 19 - I²C Setup & Hold Timing SCL S3-max S3-min SDA Figure 20 - I² ...

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... Mn_CRS_DV Symbol M2 M[7:0]_RXD[1:0] Input Setup Time M3 M[7:0]_RXD[1:0] Input Hold Time M4 M[7:0]_CRS_DV Input Setup Time M5 M[7:0]_CRS_DV Input Hold Time M6 M[7:0]_TXEN Output Delay Time M7 M[7:0]_TXD[1:0] Output Delay Time ZL50411 M_CLK M6-max M6-min Mn_TXEN M7-max M7-min Figure 21 - RMII Transmit Timing M_CLK M2 Mn_RXD Figure 22 - RMII Receive Timing ...

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... Mn_RXD[3:0] Input Setup Time MM3 Mn_RXD[3:0] Input Hold Time MM4 Mn_CRS_DV Input Setup Time MM5 Mn_CRS_DV Input Hold Time MM6 Mn_TXEN Output Delay Time MM7 Mn_TXD[3:0] Output Delay Time ZL50411 Mn_TXCLK MM6-max MM6-min Mn_TXEN MM7-max MM7-min Figure 23 - MII Transmit Timing Mn_RXCLK MM2 MM ...

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... RM6* Mn_TXEN Output Delay Time CPU_MII_TXEN Output Delay Time RM7* Mn_TXD[3:0] Output Delay Time CPU_MII_TXD[3:0] Output Delay Time * May need to add external delay depending on other MAC device’s min. hold time. ZL50411 Mn_TXCLK RM6-max RM6-min Mn_TXEN RM7-max RM7-min Figure 25 - RvMII Transmit Timing ...

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... M[7:0]_RXD Input Setup Time SM3 M[7:0]_RXD Input Hold Time SM4 M[7:0]_CRS_DV Input Setup Time SM5 M[7:0]_CRS_DV Input Hold Time SM6 M[7:0]_TXEN Output Delay Time SM7 M[7:0]_TXD Output Delay Time ZL50411 Mn_TXCLK SM6-max SM6-min Mn_TXEN SM7-max SM7-min Mn_TXD Figure 27 - GPSI Transmit Timing Mn_RXCLK SM2 ...

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... M[7:0]_CRS_DV Input Setup Time RS5 M[7:0]_CRS_DV Input Hold Time RS6* M[7:0]_TXEN Output Delay Time RS7* M[7:0]_TXD Output Delay Time * May need to add external delay depending on other MAC device’s min. hold time. ZL50411 Mn_TXCLK RS6-max RS6-min Mn_TXEN RS7-max RS7-min Mn_TXD Figure 29 - RvGPSI Transmit Timing ...

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... MII Management Data Interface (MDIO/MDC) Symbol MD1 MDIO input setup time MD2 MDIO input hold time MD3 MDIO output delay time ZL50411 MDC MD1 MD2 MDIO Figure 31 - MDIO Setup & Hold Timing MDC MD3-max MD3-min MDIO Figure 32 - MDIO Output Delay Timing ...

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... Symbol Parameter TCK frequency of operation TCK cycle time TCK clock pulse width TRST# assert time J1 TMS, TDI data setup time J2 TMS, TDI data hold time J3 TCK to TDO data valid ZL50411 J1 J2 Figure 33 - JTAG Timing Diagram Min. Typ. Max ...

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... TOP VIEW SIDE VIEW c Zarlink Semiconductor 2002 All rights reserved. 1 ISSUE 213730 ACN DATE 14Nov02 APPRD. BOTTOM VIEW b Previous package codes MIN MAX Dimension 1. 0.30 0.50 A2 0.53 REF D 16.90 17.10 16.90 17.10 E 0.40 0. 208 Conforms to JEDEC MO-192 Package Code ...

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... For more information about all Zarlink products Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use ...