zl50411 Zarlink Semiconductor, zl50411 Datasheet - Page 71

• Manufacturer Part Number: zl50411
• Description: Managed 9-port Fast Ethernet Switch With Private Vlan
• Manufacturer: Zarlink Semiconductor

CMD_STATUS_REG
CPU interface command status
This register is not applicable in SSI+MII, MII-only and Remote/No
CPU interface modes.
Bit #
[0]
[1]
[2]
[3]
[4]
[5]
[7:6]
RSVD
Name
RXBUF_DONE
RXBUF_RDY
TXBUF1_DONE
TXBUF1_RDY
TXBUF2_DONE
TXBUF2_RDY
TXFIFO_RXDONE
TXFIFO_RDY
RXFIFO_EOF
RXFIFO_SPOK
RXFIFO_REALIGN
TXFIFO_EOF
Type
W
R
W
R
W
R
W
R
W
R
W
R
R/W
Register Table 5 - 4, CMD_STATUS_REG
Zarlink Semiconductor Inc.
Description
Set Control Frame Receive buffer ready, after CPU writes a
complete frame into the buffer. This bit is self-cleared.
Control Frame receive buffer ready, CPU can write a new frame
1 – CPU can write a new control command
0 – CPU has to wait until this bit is 1 to write a new control
command
Set Control Frame Transmit buffer1 ready, after CPU reads out a
complete frame from the buffer. This bit is self-cleared.
Control Frame transmit buffer1 ready for CPU to read
1 – CPU can read a new control command 1
0 – CPU has to wait until this bit is 1 to read a new control
command
Set Control Frame Transmit buffer2 ready, after CPU reads out a
complete frame from the buffer. This bit is self-cleared.
Control Frame transmit buffer2 ready for CPU to read
1 – CPU can read a new control command 1
0 – CPU has to wait until this bit is 1 to read a new control
command
Set this bit to indicate CPU received a whole frame (transmit FIFO
frame receive done), and flushed the rest of frame fragment, If
occurs. This bit will be self-cleared.
Transmit FIFO has data for CPU to read
Set this bit to indicate that the following Write to the Receive FIFO
is the last one. This bit will be self-cleared.
Receive FIFO has space for incoming CPU frame
FIFO (re-align). This feature can be used for software debug. For
normal operation must be '0'.
Transmit FIFO End Of Frame
Reserved
Set this bit to re-start the data that is sent from the CPU to Receive
ZL50411
71
Default: 00
Width
8-bit
Access
R/W
Data Sheet
Address
4