z8fmc16100 ZiLOG Semiconductor, z8fmc16100 Datasheet - Page 85

• Manufacturer Part Number: z8fmc16100
• Description: Z8 Encore Motor Control Flash Mcus
• Manufacturer: ZiLOG Semiconductor

Table 42. PWM High Byte Register (PWMH)
BITS
FIELD
RESET
R/W
ADDR
PS024611-0408
Caution:
PWM Operation in CPU Halt Mode
PWM Operation in CPU STOP Mode
Observing the State of PWM Output Channels
PWM High and Low Byte Registers
7
When eZ8 CPU is operating in HALT mode, the PWM continues to operate, if enabled. To
minimize the current in HALT mode, the PWM must be disabled by clearing the PWMEN
bit to 0.
When the eZ8 CPU is operating in STOP mode, the PWM is disabled, as the system clock
ceases to operate in STOP mode. The PWM outputs remain in the same state as they were
prior to entering STOP mode. In normal operation, the PWM outputs must be disabled by
the software prior to the CPU entering STOP mode. A fault condition detected in STOP
mode forces the PWM outputs to a predefined OFF state.
The logic value of the PWM outputs can be sampled by reading the PWMIN register. If a
PWM channel pair is disabled (an option bit is not set), the associated PWM outputs are
forced to high-impedance, and can be used as general-purpose inputs.
The PWM High and Low Byte (PWMH and PWML) registers, shown in
Table
value in PWML to be stored in a temporary holding register. A read from PWML always
returns this temporary register value.
Writing to the PWM High and Low Byte registers while the PWM is enabled is not
recommended. There are no temporary holding registers for Write operations, so
simultaneous 12-bit Writes are not possible.
If either the PWM High register or Low Byte register are written during counting, the 8-
bit written value is placed in the counter (High or Low byte) at the next clock edge. The
counter continues counting from the new value.
43, contain the current 12-bit PWM count value. Reads from PWMH cause the
6
Reserved
R/W
0H
5
4
F2CH
3
Z8FMC16100 Series Flash MCU
PWM Operation in CPU Halt Mode
2
PWMH
R/W
Product Specification
0H
1
Table 42
0
and
73