z8fmc16100 ZiLOG Semiconductor, z8fmc16100 Datasheet - Page 184

• Manufacturer Part Number: z8fmc16100
• Description: Z8 Encore Motor Control Flash Mcus
• Manufacturer: ZiLOG Semiconductor

PS024611-0408
S
Note:
Figure 30. Data Transfer Format—Master Read Transaction with a 7-Bit Address
15. The I
16. The I
17. The I
18. If more bytes remain to be sent, return to Step 14.
19. The software responds by asserting the
20. The I
21. The I
If the slave responds with a Not Acknowledge during the transfer, the I
asserts the
halts. The software terminates the transaction by setting either the
transaction) or the
register is flushed automatically.
Master Read Transaction with a 7-Bit Address
Figure 30
The procedure for a master Read operation to a 7-bit addressed slave is as follows:
1. The software initializes the
2. The software writes the I
3. The software asserts the
4. If this operation is a single-byte transfer, the software asserts the NAK bit of the I
Slave Address
ensuing data bytes, if looping) via the SDA signal.
High period of SCL. The I
If the slave does not acknowledge, refer to the second paragraph of Step 11.
transmit interrupt asserts.
mode with 7- or 10-bit addressing (the I
address types). The
as a slave (but not for the remote slave). The software asserts the IEN bit in the I
Control register.
(which is set to 1).
Control register so that after the first byte of data has been read by the I
Not Acknowledge instruction is sent to the I
2
2
2
2
2
displays the data transfer format for a read operation to a 7-bit addressed slave.
C controller shifts out the remainder of the second byte of the slave address (or
C slave sends an Acknowledge by pulling the SDA signal Low during the next
C controller shifts the data out by the SDA signal. After the first bit is sent, the
C controller completes transmission of the data on the SDA signal.
C controller sends a
NCKI
bit, sets the
START
MODE
R = 1
bit (end this transaction, start a new one). The Transmit Data
START
2
ACKV
field selects the address width for this mode when addressed
C Data register with a 7-bit slave address, plus the Read bit
2
STOP
C controller sets the ACK bit in the I
MODE
A
bit, clears the
bit of the I
condition to the I
field in the I
Data
STOP
2
C bus protocol allows the mixing of slave
2
C Control register.
2
C slave.
bit of the I
ACK
2
C Mode register for MASTER/SLAVE
2
bit in the I
C bus.
A
2
C Control register.
Product Specification
2
Data
C State register, and
STOP
2
C Status register.
2
C controller
Master Transactions
bit (end
2
C controller, a
A
P/S
2
2
C
C
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