z8fmc16100 ZiLOG Semiconductor, z8fmc16100 Datasheet - Page 183

• Manufacturer Part Number: z8fmc16100
• Description: Z8 Encore Motor Control Flash Mcus
• Manufacturer: ZiLOG Semiconductor

PS024611-0408
Read/Write control bit (which is cleared to 0). The transmit operation is performed in the
same manner as 7-bit addressing.
The procedure for a master transmit operation to a 10-bit addressed slave is as follows:
1. The software initializes the
2. The software asserts the
3. The I
4. The software responds to the TDRE interrupt by writing the first slave address byte
5. The software asserts the
6. The I
7. The I
8. After one bit of the address is shifted out by the SDA signal, the transmit interrupt
9. The software responds by writing the second byte of address into the contents of the
10. The I
11. The I
12. The I
13. The I
14. The software responds by writing the data to be written out to the I
mode with 7- or 10-bit addressing (the I
address types). The
as a slave (but not for the remote slave). The software asserts the IEN bit in the I
Control register.
interrupts.
(
register.
asserts.
I
out via the SDA signal.
High period of SCL. The I
If the slave does not acknowledge the first address byte, the I
NCKI bit in the I
State register. The software responds to the Not Acknowledge interrupt by setting the
STOP
from the data register, sends a
NCKI
register (2nd address byte).
first bit has been sent, the transmit interrupt asserts.
11110xx0
2
C Data register.
2
2
2
2
2
2
2
bit and clearing the
bits. The transaction is complete, and the following steps can be ignored.
C interrupt asserts because the I
C controller sends a
C controller loads the I
C controller shifts the remainder of the first byte of the address and the Write bit
C slave sends an Acknowledge by pulling the SDA signal Low during the next
C controller loads the I
C controller shifts the second address byte out via the SDA signal. After the
). The least-significant bit must be 0 for the write operation.
2
C Status register, sets the
MODE
TXI
START
field selects the address width for this mode when addressed
TXI
2
START
MODE
C controller sets the ACK bit in the I
bit of the I
2
2
C Shift register with the contents of the I
C Shift register with the contents of the I
STOP
bit. The I
bit of the I
field in the I
condition to the I
condition on the bus, and clears the
2
C Data register is empty.
2
2
2
C bus protocol allows the mixing of slave
C Control register to enable transmit
C controller flushes the second address byte
2
ACKV
C Control register.
2
C Mode register for MASTER/SLAVE
bit, and clears the
2
C slave.
Product Specification
2
C controller sets the
2
C Status register.
2
Master Transactions
C Control register.
ACK
2
2
C Data
C Data
bit in the I
STOP
and
2
C
2
C
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