z8fmc16100 ZiLOG Semiconductor, z8fmc16100 Datasheet - Page 173
z8fmc16100
Manufacturer Part Number
z8fmc16100
Description
Z8 Encore Motor Control Flash Mcus
Manufacturer
ZiLOG Semiconductor
Datasheet
1.Z8FMC16100.pdf
(381 pages)
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I
PS024611-0408
2
C Master/Slave Controller
Architecture
The I
devices are bus-compatible with the I
signal (SDA) and a serial clock signal (SCL) bidirectional lines. The features of I
controller include:
•
•
•
•
•
•
•
•
•
Figure 27
Operates in MASTER/SLAVE or SLAVE ONLY modes.
Supports arbitration in a multimaster environment (MASTER/SLAVE mode).
Supports data rates up to 400 Kbps.
7-bit or 10-bit slave address recognition (interrupt only on address match).
Optional general call address recognition.
Optional digital filter on receive SDA, SCL lines.
Optional interactive receive mode allows software interpretation of each received
address and/or data byte before acknowledging.
Unrestricted number of data bytes per transfer.
Baud Rate Generator can be used as a general-purpose timer with an interrupt if the I
controller is disabled.
2
C Master/Slave Controller ensures that the Z8FMC16100 Series Flash MCU
displays the architecture of the I
2
C protocol. The I
2
C controller.
2
C bus consists of the serial data
Product Specification
Architecture
2
2
C
C
161
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